AES/UNMASKED Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	82.107us	1	1	100.00
V1	smoke	aes_smoke	4.000s	68.968us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	62.704us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	62.713us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	117.075us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	545.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	147.776us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	62.713us	20	20	100.00
		aes_csr_aliasing	10.000s	545.001us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	68.968us	50	50	100.00
		aes_config_error	6.000s	177.283us	50	50	100.00
		aes_stress	5.000s	235.422us	50	50	100.00
V2	key_length	aes_smoke	4.000s	68.968us	50	50	100.00
		aes_config_error	6.000s	177.283us	50	50	100.00
		aes_stress	5.000s	235.422us	50	50	100.00
V2	back2back	aes_stress	5.000s	235.422us	50	50	100.00
		aes_b2b	11.000s	133.204us	50	50	100.00
V2	backpressure	aes_stress	5.000s	235.422us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	68.968us	50	50	100.00
		aes_config_error	6.000s	177.283us	50	50	100.00
		aes_stress	5.000s	235.422us	50	50	100.00
		aes_alert_reset	5.000s	78.983us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	121.756us	50	50	100.00
		aes_config_error	6.000s	177.283us	50	50	100.00
		aes_alert_reset	5.000s	78.983us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	173.502us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	147.857us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	78.983us	50	50	100.00
V2	stress	aes_stress	5.000s	235.422us	50	50	100.00
V2	sideload	aes_stress	5.000s	235.422us	50	50	100.00
		aes_sideload	7.000s	200.459us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	1.273ms	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	1.861ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	81.031us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	502.220us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	502.220us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	62.704us	5	5	100.00
		aes_csr_rw	6.000s	62.713us	20	20	100.00
		aes_csr_aliasing	10.000s	545.001us	5	5	100.00
		aes_same_csr_outstanding	9.000s	79.274us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	62.704us	5	5	100.00
		aes_csr_rw	6.000s	62.713us	20	20	100.00
		aes_csr_aliasing	10.000s	545.001us	5	5	100.00
		aes_same_csr_outstanding	9.000s	79.274us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	468.419us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	113.195us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	3.193ms	5	5	100.00
		aes_tl_intg_err	8.000s	144.320us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	144.320us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	78.983us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	68.968us	50	50	100.00
		aes_stress	5.000s	235.422us	50	50	100.00
		aes_alert_reset	5.000s	78.983us	50	50	100.00
		aes_core_fi	5.933m	10.010ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	177.024us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	81.390us	50	50	100.00
		aes_stress	5.000s	235.422us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	235.422us	50	50	100.00
		aes_sideload	7.000s	200.459us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	81.390us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	81.390us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	81.390us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	81.390us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	81.390us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	235.422us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	235.422us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	1.428ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	1.428ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	35.033ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	1.428ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	78.983us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_ctr_fi	4.000s	71.063us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	1.428ms	50	50	100.00
		aes_control_fi	50.000s	31.536ms	271	300	90.33
		aes_cipher_fi	52.000s	35.033ms	328	350	93.71
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.300m	76.464ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1535	1602	95.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	97.40	94.16	98.79	93.53	97.72	91.11	98.85	95.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 16 failures.
  - 10.aes_control_fi.41498314114201760167214735201203091506968067298473205185730717422042164253040
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:17d4aa33-720e-4c73-a871-fbda26c79b05
```
  - 13.aes_control_fi.110178047260464851273015045050022508324598118506960726630143782968380694409595
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:fda8b412-5b67-45b0-a51e-cced8aa884bf
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 12 failures.
  - 36.aes_cipher_fi.62257474271306641784894990183496287557776957850410628594829556799077229743206
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4ea6e445-b821-4eff-8f8a-0638d1f1a3d1
```
  - 90.aes_cipher_fi.5942146513648634062844035136961383055101860131638002376085857652151587982153
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  Job ID: smart:eb834d46-f054-46c2-91d1-da767ee83736
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 30.aes_control_fi.84682885453628179239267911759265911174339380265949819900042038179747673732362
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010371281 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010371281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 155.aes_control_fi.113908307929012399660476800005557528346736016965105962992736624368349673810112
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/155.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015411700 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015411700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 33.aes_cipher_fi.28750742015986547743294113626845349861345814284988853168961789903014941859586
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005544198 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005544198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 82.aes_cipher_fi.12201648097070702477749290230154259276827054309562604844765617836115183010435
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/82.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007282909 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007282909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.103841439661816675569711440400708249218726303345115646590267079589739046314230
Line 1312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1276211126 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1276211126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.91132714816888553286477634945840785088501044443944225840418348561232500868427
Line 611, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 116247523 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 116247523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.58000517430883139731056550708881806623138620862571177048609909921080180338800
Line 757, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 378082550 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 378082550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.84473444730192647858083838978302131044421163307656768935369142387963108985400
Line 857, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 381176674 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 381176674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 1.aes_core_fi.39538236885056603857100007886778448114196960268622949570460948539377793768683
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012520643 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012520643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_core_fi.2236257517425106044227264371311044745699629377132776322908524226557284457328
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002165806 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002165806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 19.aes_core_fi.13101105369691526862079082702318172635217612183069902867005479438651250971804
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008546756 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008546756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.aes_core_fi.96325807578245398579058287782962274831381578840749026889756781039168893411606
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020992154 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020992154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 23.aes_core_fi.59517526164887520780277127924151412645562410907590358517414045522204991297424
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010330314 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5425bd84) == 0x0
  UVM_INFO @ 10010330314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_core_fi.42104122045356971029122384102330191867479266068739029311338015738703484627768
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030540921 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x63944484) == 0x0
  UVM_INFO @ 10030540921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 184.aes_cipher_fi.85936551458863403243925817411340702600946141456406366698026184589510592905503
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/184.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 201.aes_cipher_fi.63251210083179303635780773305995090455898011850462116383749083952198396562593
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/201.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  43923707 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  43923707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```