AES/UNMASKED Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	69.098us	1	1	100.00
V1	smoke	aes_smoke	9.000s	69.968us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	151.368us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	224.706us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	2.209ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	251.684us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	90.694us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	224.706us	20	20	100.00
		aes_csr_aliasing	5.000s	251.684us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	69.968us	50	50	100.00
		aes_config_error	7.000s	58.459us	50	50	100.00
		aes_stress	13.000s	68.622us	50	50	100.00
V2	key_length	aes_smoke	9.000s	69.968us	50	50	100.00
		aes_config_error	7.000s	58.459us	50	50	100.00
		aes_stress	13.000s	68.622us	50	50	100.00
V2	back2back	aes_stress	13.000s	68.622us	50	50	100.00
		aes_b2b	11.000s	967.798us	50	50	100.00
V2	backpressure	aes_stress	13.000s	68.622us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	69.968us	50	50	100.00
		aes_config_error	7.000s	58.459us	50	50	100.00
		aes_stress	13.000s	68.622us	50	50	100.00
		aes_alert_reset	9.000s	139.124us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	81.910us	50	50	100.00
		aes_config_error	7.000s	58.459us	50	50	100.00
		aes_alert_reset	9.000s	139.124us	49	50	98.00
V2	trigger_clear_test	aes_clear	8.000s	155.278us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	272.143us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	139.124us	49	50	98.00
V2	stress	aes_stress	13.000s	68.622us	50	50	100.00
V2	sideload	aes_stress	13.000s	68.622us	50	50	100.00
		aes_sideload	9.000s	78.035us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	167.020us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	4.118ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	72.161us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	613.132us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	613.132us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	151.368us	5	5	100.00
		aes_csr_rw	3.000s	224.706us	20	20	100.00
		aes_csr_aliasing	5.000s	251.684us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.208ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	151.368us	5	5	100.00
		aes_csr_rw	3.000s	224.706us	20	20	100.00
		aes_csr_aliasing	5.000s	251.684us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.208ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	9.000s	104.112us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.000m	10.170ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.474ms	5	5	100.00
		aes_tl_intg_err	5.000s	153.813us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	153.813us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	139.124us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	69.968us	50	50	100.00
		aes_stress	13.000s	68.622us	50	50	100.00
		aes_alert_reset	9.000s	139.124us	49	50	98.00
		aes_core_fi	52.000s	10.008ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	73.106us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	81.967us	50	50	100.00
		aes_stress	13.000s	68.622us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	68.622us	50	50	100.00
		aes_sideload	9.000s	78.035us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	81.967us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	81.967us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	81.967us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	81.967us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	81.967us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	68.622us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	68.622us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	147.971us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	147.971us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	16.443ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	147.971us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	139.124us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_ctr_fi	9.000s	88.276us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	147.971us	50	50	100.00
		aes_control_fi	49.000s	65.645ms	282	300	94.00
		aes_cipher_fi	51.000s	16.443ms	323	350	92.29
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.467m	5.952ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.40	94.13	98.87	93.54	97.64	93.33	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 14 failures.
  - 30.aes_control_fi.13074510670635649748545455772021510611249285335355776913855915601124652179724
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:37aea23d-6cb3-4116-b2b6-8fdeb7523350
```
  - 56.aes_control_fi.30348848474904166564342726432040724594905307315413727608994671544854034172680
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job ID: smart:084443db-7285-492f-a801-b8f511ce2b45
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 15 failures.
  - 65.aes_cipher_fi.10773811462160553575947794256997856256397438617938386336421624324991376829143
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  Job ID: smart:915cd8a2-0408-407d-b5a1-beb48435bb48
```
  - 99.aes_cipher_fi.42102196836301500148901534739553689070590440440475642901438772609316569446216
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/99.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cb39a43e-662d-48fd-ac9a-37db1a048872
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 15.aes_cipher_fi.7049364578179422271133019650535718993224522757467114572892696353407569570186
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006199725 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006199725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_cipher_fi.38464776585871090328084181847047887337176954634587543653190792599870714668198
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008723003 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008723003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.7487380281586561905352760452466114958981602268842117082893981563152799794411
Line 379, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  93951148 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  93951148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.24157899515977502440501910283872356578334505912716104909850156959886145657383
Line 820, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2481564019 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2481564019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 14.aes_core_fi.85604404366235861659439906454885308156858775575568892329439760501403427757794
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009660653 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009660653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_core_fi.65984334789280719361358608253515528701557451909854380586157727353052675034091
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011901661 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011901661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 125.aes_control_fi.3333761841147456720128306483137531813427847529971771208882507614027133059468
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/125.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10001781644 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001781644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 188.aes_control_fi.62288823765377515469160896056092729038642845304202072845763806758142856354303
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/188.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006465092 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006465092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.67692285335896248947324118713246805800218892715289020712687196039729166519454
Line 1272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1306548635 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1306548635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.92539870006279687950149689056075414659260505229208024843579259220165950202273
Line 508, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1175102493 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1175102493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 0.aes_same_csr_outstanding.28907680255612337440595756406491417277420964437374013929212133459179990586810
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10208347889 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xd121e284) == 0x0
  UVM_INFO @ 10208347889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 7.aes_shadow_reg_errors_with_csr_rw.39696524411561571023861520854512413253923646552557713448856334567545829679640
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10170013950 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x94ffe984) == 0x0
  UVM_INFO @ 10170013950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 14.aes_alert_reset.65999605592316919309778858893133041872490933660092066820551440766498146599606
    Line 629, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 12332992 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 12289514 PS)
  UVM_ERROR @  12332992 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  12332992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 46.aes_core_fi.72504176662962102860599929494053154102422709027643644481196656671689171125194
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007764198 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007764198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```