AES/UNMASKED Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	61.297us	1	1	100.00
V1	smoke	aes_smoke	9.000s	58.987us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	56.852us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	85.533us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	18.000s	1.685ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	13.000s	72.115us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	107.494us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	85.533us	20	20	100.00
		aes_csr_aliasing	13.000s	72.115us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	9.000s	58.987us	50	50	100.00
		aes_config_error	9.000s	491.106us	50	50	100.00
		aes_stress	10.000s	214.158us	50	50	100.00
V2	key_length	aes_smoke	9.000s	58.987us	50	50	100.00
		aes_config_error	9.000s	491.106us	50	50	100.00
		aes_stress	10.000s	214.158us	50	50	100.00
V2	back2back	aes_stress	10.000s	214.158us	50	50	100.00
		aes_b2b	10.000s	130.229us	50	50	100.00
V2	backpressure	aes_stress	10.000s	214.158us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	58.987us	50	50	100.00
		aes_config_error	9.000s	491.106us	50	50	100.00
		aes_stress	10.000s	214.158us	50	50	100.00
		aes_alert_reset	9.000s	90.986us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	61.387us	50	50	100.00
		aes_config_error	9.000s	491.106us	50	50	100.00
		aes_alert_reset	9.000s	90.986us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	316.023us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	196.827us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	90.986us	50	50	100.00
V2	stress	aes_stress	10.000s	214.158us	50	50	100.00
V2	sideload	aes_stress	10.000s	214.158us	50	50	100.00
		aes_sideload	6.000s	909.658us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	92.307us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	5.781ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	75.437us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	12.000s	136.408us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	12.000s	136.408us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	56.852us	5	5	100.00
		aes_csr_rw	8.000s	85.533us	20	20	100.00
		aes_csr_aliasing	13.000s	72.115us	5	5	100.00
		aes_same_csr_outstanding	15.000s	173.108us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	56.852us	5	5	100.00
		aes_csr_rw	8.000s	85.533us	20	20	100.00
		aes_csr_aliasing	13.000s	72.115us	5	5	100.00
		aes_same_csr_outstanding	15.000s	173.108us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	190.068us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	99.605us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.199ms	5	5	100.00
		aes_tl_intg_err	11.000s	534.753us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	11.000s	534.753us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	90.986us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	58.987us	50	50	100.00
		aes_stress	10.000s	214.158us	50	50	100.00
		aes_alert_reset	9.000s	90.986us	50	50	100.00
		aes_core_fi	1.683m	10.033ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	76.504us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	57.119us	50	50	100.00
		aes_stress	10.000s	214.158us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	214.158us	50	50	100.00
		aes_sideload	6.000s	909.658us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	57.119us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	57.119us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	57.119us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	57.119us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	57.119us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	214.158us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	214.158us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	544.628us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	544.628us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	16.271ms	316	350	90.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	544.628us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	90.986us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_ctr_fi	8.000s	63.537us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	544.628us	48	50	96.00
		aes_control_fi	51.000s	10.002ms	270	300	90.00
		aes_cipher_fi	49.000s	16.271ms	316	350	90.29
V2S		TOTAL			917	985	93.10
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	36.000s	1.483ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1523	1602	95.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.39	94.09	98.85	93.68	97.64	91.85	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 43 failures:
- Test aes_cipher_fi has 24 failures.
  - 4.aes_cipher_fi.61779886317191808553520614197551155121477337342370000426418001403635931977809
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:20609e7b-e938-4c69-bc98-3bbbaa5a405c
```
  - 41.aes_cipher_fi.48553693173822338685757161854698071370093544610169283638205909619777525151098
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  Job ID: smart:484548b0-fe4d-44c6-98c3-9e7643abe174
```
  - ... and 22 more failures.
- Test aes_control_fi has 19 failures.
  - 30.aes_control_fi.61357981460272610627015666738574606636013579270278593066329234285594306320728
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:59fa4351-2b19-40f3-88a6-c7b870c5768a
```
  - 72.aes_control_fi.110350789607169447963756377421067599451996140827900633000327015602004081234204
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  Job ID: smart:1d2d90a9-ee32-49b2-bcda-5d85f15b1fc2
```
  - ... and 17 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 11.aes_control_fi.65336294451657079904724581488766076089777208451224589709254145434260912088301
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005419163 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005419163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_control_fi.14279007998906209150096273466880184453994215417839463033099651365225830607860
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023736033 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023736033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 5.aes_cipher_fi.66075341483790462172221757441340011083243272883987807293635835226112102398724
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10117259931 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10117259931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_cipher_fi.65663010144295385038121161241674852130390546631414352660267332600129093657606
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012248467 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012248467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.108784598655398707479084257012224940851632094616717615891523383044703791542042
Line 1006, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 438174979 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 438174979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.34238512480271513795652109462215514409337989912717318370445268621040046230474
Line 1549, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4172001270 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4172001270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

5.aes_stress_all_with_rand_reset.77299663218289885687262408136123095299655152671205099948903150891416311975571
Line 699, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 300226528 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 300226528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.13466337278753552483862903222374892980401919892708036969111861723825703209601
Line 750, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 308800220 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 308800220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

6.aes_stress_all_with_rand_reset.18158203317049097374554222228368012370147431264789117274821217296444093684541
Line 1122, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 256192038 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 256182038 PS)
  UVM_ERROR @ 256192038 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 256192038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

10.aes_fi.32542848443649284020547619880821920997508707804581441406734721041779555566552
Line 4155, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 21027975 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21007975 PS)
  UVM_ERROR @  21027975 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  21027975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.aes_csr_mem_rw_with_rand_reset.63210358342560986029105703588673290076872709820858040111577440837950023722605
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 243068053 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 243068053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 7.aes_core_fi.91413221426037483543400358326077091561467333433036080236183893009774969867499
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032902981 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xcacd6884) == 0x0
  UVM_INFO @ 10032902981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 31.aes_fi.52235847541327801308905808631870668924498834774140393036073418747999738689411
    Line 8781, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_fi/latest/run.log
```
  UVM_FATAL @  44618099 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  44618099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.97993231754366153420248374839722888720366287302706358257612561167625681485504
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013250780 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013250780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```