AES/UNMASKED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	70.857us	1	1	100.00
V1	smoke	aes_smoke	13.000s	76.788us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	54.315us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	67.226us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.984ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	198.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	12.000s	54.646us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	67.226us	20	20	100.00
		aes_csr_aliasing	9.000s	198.363us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	13.000s	76.788us	50	50	100.00
		aes_config_error	18.000s	79.647us	50	50	100.00
		aes_stress	19.000s	69.006us	50	50	100.00
V2	key_length	aes_smoke	13.000s	76.788us	50	50	100.00
		aes_config_error	18.000s	79.647us	50	50	100.00
		aes_stress	19.000s	69.006us	50	50	100.00
V2	back2back	aes_stress	19.000s	69.006us	50	50	100.00
		aes_b2b	17.000s	276.590us	50	50	100.00
V2	backpressure	aes_stress	19.000s	69.006us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	76.788us	50	50	100.00
		aes_config_error	18.000s	79.647us	50	50	100.00
		aes_stress	19.000s	69.006us	50	50	100.00
		aes_alert_reset	9.000s	511.026us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	116.584us	50	50	100.00
		aes_config_error	18.000s	79.647us	50	50	100.00
		aes_alert_reset	9.000s	511.026us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	108.967us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	226.770us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	511.026us	50	50	100.00
V2	stress	aes_stress	19.000s	69.006us	50	50	100.00
V2	sideload	aes_stress	19.000s	69.006us	50	50	100.00
		aes_sideload	19.000s	169.114us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	59.461us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	1.054ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	86.709us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	19.000s	123.668us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	19.000s	123.668us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	54.315us	5	5	100.00
		aes_csr_rw	13.000s	67.226us	20	20	100.00
		aes_csr_aliasing	9.000s	198.363us	5	5	100.00
		aes_same_csr_outstanding	10.000s	86.624us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	54.315us	5	5	100.00
		aes_csr_rw	13.000s	67.226us	20	20	100.00
		aes_csr_aliasing	9.000s	198.363us	5	5	100.00
		aes_same_csr_outstanding	10.000s	86.624us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	19.000s	82.644us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	456.711us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	492.941us	5	5	100.00
		aes_tl_intg_err	9.000s	199.181us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	199.181us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	511.026us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	76.788us	50	50	100.00
		aes_stress	19.000s	69.006us	50	50	100.00
		aes_alert_reset	9.000s	511.026us	50	50	100.00
		aes_core_fi	6.933m	10.012ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	23.000s	86.812us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	70.407us	50	50	100.00
		aes_stress	19.000s	69.006us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	69.006us	50	50	100.00
		aes_sideload	19.000s	169.114us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	70.407us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	70.407us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	70.407us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	70.407us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	70.407us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	69.006us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	69.006us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	78.491us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	78.491us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.018ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	78.491us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	511.026us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_ctr_fi	9.000s	63.342us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	78.491us	50	50	100.00
		aes_control_fi	45.000s	16.445ms	282	300	94.00
		aes_cipher_fi	51.000s	10.018ms	324	350	92.57
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.450m	7.260ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.39	94.09	98.83	93.65	97.72	91.11	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 9 failures.
  - 43.aes_control_fi.14679703391467743205808414355300086485696263039490076182624609459035002797466
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:85434a1c-b48d-468b-b45e-4238937bf612
```
  - 45.aes_control_fi.26592207665640913010935059672238676499935136595363301949456852808373678685694
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:d78366a2-fb9c-4897-8fb7-74a62bd42efe
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 16 failures.
  - 59.aes_cipher_fi.75660565662805032264784201072657035020962186597614167671452964017078826155072
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job ID: smart:37dc5b42-89ed-40b6-846d-a681dbd4a08b
```
  - 66.aes_cipher_fi.91219987862641384582471386278938931051659358408127420165076190828123943768422
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:499ecf4d-d165-41a5-bae5-474db186952c
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 57.aes_cipher_fi.20828230761248081882820807514417673630961878841636618916025501876379148727166
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021913411 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021913411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 158.aes_cipher_fi.21698057073380541524815213261673622248312670528066728557509856449554053474175
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/158.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009980444 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009980444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 14.aes_control_fi.2305614651707382013807820494672034761855536209811886496510803644010823673419
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004254441 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004254441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_control_fi.88802398401122451043013934824438659880804686774954815485837993629733623761239
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009577053 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009577053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.11442572230204484829019191175748447815268555918739487256853731595957570783721
Line 1682, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 548238812 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 548238812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.102109869099719935208679424840855939126874181905812088889089450706855478615014
Line 1291, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 661628761 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 661628761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.55908135513080105378291208171362490181400961488703617754389548192995401350216
Line 1459, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 717294418 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 717294418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.81709793668551881089131630419365026592192058058592127024635801403034670049873
Line 1603, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 436164411 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 436164411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 3 failures:
- Test aes_core_fi has 3 failures.
  - 17.aes_core_fi.67287264394461591172704526907057287297019458257273789995958234914331870117432
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024267467 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xaa11e184) == 0x0
  UVM_INFO @ 10024267467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_core_fi.5725446633257502037795662524362167512844549125247864390129638135870060301958
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10029037567 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf07b8284) == 0x0
  UVM_INFO @ 10029037567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 33.aes_core_fi.21884076580728127985788851396806909937611906343146087959165130091310072220992
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005914721 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005914721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_core_fi.60282362012351533617059635098123310971836310471194389111060808559316892719802
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021901617 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021901617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.37242288063800993544611759938067665147411641408256451886350933147145381874717
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  71507042 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  71507042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

9.aes_stress_all.22657248911558335800353341631612981608812773743888538422814063407542555971695
Line 1172, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 12219823 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 12209722 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 12219823 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 12209722 PS)
  UVM_ERROR @  12219823 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.aes_csr_mem_rw_with_rand_reset.29256373710333128848667394966355339536612462319775721436788117718053812878108
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 298453238 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 298453238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 56.aes_core_fi.105720293831263627359111790478302140264053785120003388878302909543549729096697
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009430318 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009430318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```