AES/UNMASKED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.535us	1	1	100.00
V1	smoke	aes_smoke	4.000s	115.786us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	90.830us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	93.038us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	15.000s	3.048ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	370.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	103.581us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	93.038us	20	20	100.00
		aes_csr_aliasing	5.000s	370.720us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	115.786us	50	50	100.00
		aes_config_error	5.000s	324.591us	50	50	100.00
		aes_stress	9.000s	226.725us	50	50	100.00
V2	key_length	aes_smoke	4.000s	115.786us	50	50	100.00
		aes_config_error	5.000s	324.591us	50	50	100.00
		aes_stress	9.000s	226.725us	50	50	100.00
V2	back2back	aes_stress	9.000s	226.725us	50	50	100.00
		aes_b2b	12.000s	159.017us	50	50	100.00
V2	backpressure	aes_stress	9.000s	226.725us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	115.786us	50	50	100.00
		aes_config_error	5.000s	324.591us	50	50	100.00
		aes_stress	9.000s	226.725us	50	50	100.00
		aes_alert_reset	9.000s	156.871us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	52.122us	50	50	100.00
		aes_config_error	5.000s	324.591us	50	50	100.00
		aes_alert_reset	9.000s	156.871us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	167.146us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	406.180us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	156.871us	50	50	100.00
V2	stress	aes_stress	9.000s	226.725us	50	50	100.00
V2	sideload	aes_stress	9.000s	226.725us	50	50	100.00
		aes_sideload	8.000s	153.022us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	56.701us	50	50	100.00
V2	stress_all	aes_stress_all	43.000s	12.835ms	9	10	90.00
V2	alert_test	aes_alert_test	7.000s	61.106us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	2.279ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	2.279ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	90.830us	5	5	100.00
		aes_csr_rw	3.000s	93.038us	20	20	100.00
		aes_csr_aliasing	5.000s	370.720us	5	5	100.00
		aes_same_csr_outstanding	4.000s	142.546us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	90.830us	5	5	100.00
		aes_csr_rw	3.000s	93.038us	20	20	100.00
		aes_csr_aliasing	5.000s	370.720us	5	5	100.00
		aes_same_csr_outstanding	4.000s	142.546us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	10.000s	111.567us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	167.361us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	857.329us	5	5	100.00
		aes_tl_intg_err	5.000s	518.037us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	518.037us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	156.871us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	115.786us	50	50	100.00
		aes_stress	9.000s	226.725us	50	50	100.00
		aes_alert_reset	9.000s	156.871us	50	50	100.00
		aes_core_fi	3.567m	10.013ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	122.247us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	55.583us	50	50	100.00
		aes_stress	9.000s	226.725us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	226.725us	50	50	100.00
		aes_sideload	8.000s	153.022us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	55.583us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	55.583us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	55.583us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	55.583us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	55.583us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	226.725us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	226.725us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	217.811us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	217.811us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	38.437ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	217.811us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	156.871us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_ctr_fi	9.000s	63.117us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	217.811us	50	50	100.00
		aes_control_fi	49.000s	16.274ms	274	300	91.33
		aes_cipher_fi	50.000s	38.437ms	330	350	94.29
V2S		TOTAL			937	985	95.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.917m	19.760ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.46	94.25	98.87	93.68	97.64	93.33	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 19 failures.
  - 1.aes_control_fi.8787688768796982093302000811965713437745014502945124683589762787122834978825
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:62cba4db-2716-4b39-b947-c1e66f7288a8
```
  - 6.aes_control_fi.110127064016104950093640846560048559050426832290440191111002124772223907395984
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:4034b662-cbdb-4c5d-a3cf-4d2c1d473b54
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 11 failures.
  - 9.aes_cipher_fi.111441811725970085413803839991163822570658334126504780425260348795522407313744
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:93f6919e-d457-4647-a8f6-299abd6a3a7b
```
  - 57.aes_cipher_fi.95029389768678673700811835363430506826781513625775084632573716909911360307953
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e1708329-ec62-46b0-9142-48981dd9851a
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 33.aes_cipher_fi.81277080205204933780773659077719957027131873843634467321482310748975696499454
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004727290 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004727290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_cipher_fi.76943897207600888336477328862447443023387413016734410411261313641126187022025
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014861977 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014861977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.75486729743189686026365923479488444994066448007137508155778064424496946352136
Line 1303, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1293349082 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1293349082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.19153662017578684405544165270730878094759617943787309297956907110956405857261
Line 1836, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14539256275 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 14539256275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 0.aes_control_fi.58434706794993118013256939835243442157305698635325729798949599451821628344237
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010627791 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010627791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_control_fi.30665675289046575919377985476626132591121685385217153486143191528278068791743
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007462428 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007462428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 0.aes_stress_all.53469691785997128514887462321179342195147059542173211347377753090404742646064
    Line 1469, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 15527997 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 15517580 PS)
  UVM_ERROR @  15527997 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  15527997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.43459764928375345811094363562971994167151231921008249024009073425276154469434
    Line 1341, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 686281635 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 686281635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.35070108290399564903227013923089963239135859714758316417694800894346221493728
    Line 456, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 295180614 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 295180614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.13000791293307264262931327777422778487836772691838969814646303395029688789335
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012885184 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x86e01384) == 0x0
  UVM_INFO @ 10012885184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 16.aes_core_fi.9349912080112705975550095656884842101881211266507988447075231138464803677101
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005706563 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005706563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```