AES/UNMASKED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	104.484us	1	1	100.00
V1	smoke	aes_smoke	13.000s	73.733us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	55.521us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	67.632us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	508.802us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	223.273us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	98.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	67.632us	20	20	100.00
		aes_csr_aliasing	5.000s	223.273us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	73.733us	50	50	100.00
		aes_config_error	13.000s	115.047us	50	50	100.00
		aes_stress	10.000s	239.399us	50	50	100.00
V2	key_length	aes_smoke	13.000s	73.733us	50	50	100.00
		aes_config_error	13.000s	115.047us	50	50	100.00
		aes_stress	10.000s	239.399us	50	50	100.00
V2	back2back	aes_stress	10.000s	239.399us	50	50	100.00
		aes_b2b	14.000s	137.480us	50	50	100.00
V2	backpressure	aes_stress	10.000s	239.399us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	73.733us	50	50	100.00
		aes_config_error	13.000s	115.047us	50	50	100.00
		aes_stress	10.000s	239.399us	50	50	100.00
		aes_alert_reset	11.000s	189.507us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	117.821us	50	50	100.00
		aes_config_error	13.000s	115.047us	50	50	100.00
		aes_alert_reset	11.000s	189.507us	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	80.272us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	171.996us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	189.507us	50	50	100.00
V2	stress	aes_stress	10.000s	239.399us	50	50	100.00
V2	sideload	aes_stress	10.000s	239.399us	50	50	100.00
		aes_sideload	24.000s	123.124us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	113.763us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	3.158ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	132.374us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	111.568us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	111.568us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	55.521us	5	5	100.00
		aes_csr_rw	13.000s	67.632us	20	20	100.00
		aes_csr_aliasing	5.000s	223.273us	5	5	100.00
		aes_same_csr_outstanding	8.000s	63.305us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	55.521us	5	5	100.00
		aes_csr_rw	13.000s	67.632us	20	20	100.00
		aes_csr_aliasing	5.000s	223.273us	5	5	100.00
		aes_same_csr_outstanding	8.000s	63.305us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	11.000s	170.216us	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	317.973us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.461ms	5	5	100.00
		aes_tl_intg_err	11.000s	753.645us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	11.000s	753.645us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	189.507us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	73.733us	50	50	100.00
		aes_stress	10.000s	239.399us	50	50	100.00
		aes_alert_reset	11.000s	189.507us	50	50	100.00
		aes_core_fi	6.567m	10.011ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	138.463us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	57.215us	50	50	100.00
		aes_stress	10.000s	239.399us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	239.399us	50	50	100.00
		aes_sideload	24.000s	123.124us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	57.215us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	57.215us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	57.215us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	57.215us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	57.215us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	239.399us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	239.399us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	75.681us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	75.681us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	24.645ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	75.681us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	189.507us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_ctr_fi	13.000s	95.795us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	75.681us	49	50	98.00
		aes_control_fi	49.000s	65.626ms	277	300	92.33
		aes_cipher_fi	50.000s	24.645ms	332	350	94.86
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	9.283m	62.748ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1545	1602	96.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.25	97.55	94.48	98.81	93.74	97.72	93.33	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_cipher_fi has 11 failures.
  - 2.aes_cipher_fi.15254954908378465836835141085715438689109609580962951119512658565382798219145
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:45702792-4375-410c-b8bb-21b23c07e9ec
```
  - 80.aes_cipher_fi.22602985418551909173357168643462740310785818801860861082290253657234772756168
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/80.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b900bdd5-fdc6-494d-8a05-56c18c44074e
```
  - ... and 9 more failures.
- Test aes_control_fi has 11 failures.
  - 25.aes_control_fi.25392726122492094587646467903032022934349692565222700553072019010692831835599
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:c6afdd78-72f7-43ee-929d-e9964e620f7e
```
  - 33.aes_control_fi.65582156817047391050125397829499192370949075432480933246458046063351498641081
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job ID: smart:7729c5aa-020e-4e92-a8f9-f8f3bcd02852
```
  - ... and 9 more failures.
- Test aes_ctr_fi has 1 failures.
  - 29.aes_ctr_fi.34020256157289683014541245220745328539476362029250051744050882167090188228013
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job ID: smart:8ec600f4-67be-4a1f-ad6d-e44bce830ba8
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.99281515174486300465932777715912678412052330116747917163802970413865302572967
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005502776 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005502776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_control_fi.73989144253186623327976600484784592247903650388669415518511531326880153463443
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003124444 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003124444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 47.aes_cipher_fi.35236863190366555816164675529540324356870336374478313757747059969984462540703
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012288275 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012288275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 95.aes_cipher_fi.94619193337376662398139509333527327161862623516190732654951225040931865411877
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/95.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007378505 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007378505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.62521886940489360808508993677941005041734530772513862257637463712295457475657
Line 1073, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 522872654 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 522872654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.94342982174702809687864423724482272537420377630948238971443858167644650156673
Line 637, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 321503759 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 321503759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

5.aes_stress_all_with_rand_reset.28113427941459468209689701078518383278403221649076205717107003593209257870376
Line 1536, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 409598578 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 409598578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.17096003056884084511089273299088995798871213870527064517048941002691565466502
Line 1534, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1673197816 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1673197816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 16.aes_core_fi.49230064015430919770871304263962895490470672795071711812584708750165271152443
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006537378 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006537378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_core_fi.28576026971898997459933751382434762067518262338962492939580405693215820572943
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005512561 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005512561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 30.aes_core_fi.54249004367771302443127987637753688733589140838337189828636874756245753040961
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016394721 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x42c68584) == 0x0
  UVM_INFO @ 10016394721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_core_fi.39162117318540476360053507401999391920906615251140304514861861663921496235336
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010781940 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x19e29884) == 0x0
  UVM_INFO @ 10010781940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.89681276653323011494777645750423004923880746772151209811586998906488957165772
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  39882638 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  39882638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 11.aes_fi.15579547718394563835783121052980055486752166733512358290042459540134198588814
    Line 7649, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_fi/latest/run.log
```
  UVM_FATAL @  41278448 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  41278448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```