AES/UNMASKED Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	116.215us	1	1	100.00
V1	smoke	aes_smoke	5.000s	337.751us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.536us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	138.937us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.985ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	1.640ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	234.565us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	138.937us	20	20	100.00
		aes_csr_aliasing	6.000s	1.640ms	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	5.000s	337.751us	50	50	100.00
		aes_config_error	5.000s	109.320us	50	50	100.00
		aes_stress	5.000s	207.467us	50	50	100.00
V2	key_length	aes_smoke	5.000s	337.751us	50	50	100.00
		aes_config_error	5.000s	109.320us	50	50	100.00
		aes_stress	5.000s	207.467us	50	50	100.00
V2	back2back	aes_stress	5.000s	207.467us	50	50	100.00
		aes_b2b	10.000s	139.905us	50	50	100.00
V2	backpressure	aes_stress	5.000s	207.467us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	337.751us	50	50	100.00
		aes_config_error	5.000s	109.320us	50	50	100.00
		aes_stress	5.000s	207.467us	50	50	100.00
		aes_alert_reset	5.000s	134.602us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	80.568us	50	50	100.00
		aes_config_error	5.000s	109.320us	50	50	100.00
		aes_alert_reset	5.000s	134.602us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	1.100ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	412.256us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	134.602us	50	50	100.00
V2	stress	aes_stress	5.000s	207.467us	50	50	100.00
V2	sideload	aes_stress	5.000s	207.467us	50	50	100.00
		aes_sideload	5.000s	140.731us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	163.034us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	523.886us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	61.420us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	297.611us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	297.611us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.536us	5	5	100.00
		aes_csr_rw	3.000s	138.937us	20	20	100.00
		aes_csr_aliasing	6.000s	1.640ms	5	5	100.00
		aes_same_csr_outstanding	54.000s	10.078ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.536us	5	5	100.00
		aes_csr_rw	3.000s	138.937us	20	20	100.00
		aes_csr_aliasing	6.000s	1.640ms	5	5	100.00
		aes_same_csr_outstanding	54.000s	10.078ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	546.252us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	91.635us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.960ms	5	5	100.00
		aes_tl_intg_err	5.000s	156.219us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	156.219us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	134.602us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	337.751us	50	50	100.00
		aes_stress	5.000s	207.467us	50	50	100.00
		aes_alert_reset	5.000s	134.602us	50	50	100.00
		aes_core_fi	4.450m	10.014ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	95.467us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	56.968us	50	50	100.00
		aes_stress	5.000s	207.467us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	207.467us	50	50	100.00
		aes_sideload	5.000s	140.731us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	56.968us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	56.968us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	56.968us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	56.968us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	56.968us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	207.467us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	207.467us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	158.321us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	158.321us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	32.165ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	158.321us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	134.602us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_ctr_fi	4.000s	54.011us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	158.321us	49	50	98.00
		aes_control_fi	48.000s	32.843ms	277	300	92.33
		aes_cipher_fi	50.000s	32.165ms	330	350	94.29
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.017m	19.455ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.54	94.43	98.79	93.74	97.64	91.11	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 17 failures.
  - 5.aes_control_fi.58100963832337841000469023846203806877783656849199722866273924511929662982728
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:0d7591aa-5b17-4e7d-aaf7-0d293ba85093
```
  - 49.aes_control_fi.2574962292749648444247706937813345630163015611820068001853510424598350041463
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job ID: smart:f82e127d-b9fc-4722-aa03-b32ad5cec0d1
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 5.aes_ctr_fi.23689367906259653709489822381362747771187041122176502352341302423627770028497
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_ctr_fi/latest/run.log
```
  Job ID: smart:5dcd2ebe-13a6-4ae2-bb7e-d7b40ce8fc31
```
- Test aes_cipher_fi has 12 failures.
  - 25.aes_cipher_fi.78388920437382334310806720556486201397971514404226162028231838743892559164098
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c166db4e-fa71-4c4b-b82b-a3e2a0bf6d80
```
  - 66.aes_cipher_fi.34174745846701660405777601416122242100707335406819810861110900067204098861450
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4ae18a42-b13f-4053-b6f2-b20f8767e8e1
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 6.aes_cipher_fi.76189501508912270361998631646765268293228607331639128339915218895131482178609
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006346153 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006346153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.aes_cipher_fi.78419302666895018306370193712317027977440137853358292012227377790291928965914
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014515235 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014515235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.94190323477573090356430133558709204652713558887109285648572431184073946130464
Line 1251, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15490761167 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15490761167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.97966807138450412092622865963931662626047008147446418328671516814060719234965
Line 523, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19454853488 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 19454853488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 28.aes_control_fi.17822118285765845245743302323628590297779790348810721536081219573957844681142
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003563560 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003563560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 73.aes_control_fi.52791399870691787060599812377075050361350339385792860400456548171576396734565
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/73.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006922117 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006922117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.78886274767151816443808366548968512700880872771709081792173820309472914184936
Line 1805, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2243373217 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2243373217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.14054181746441994705061368624382354083839120657077011326926282470302595257719
Line 756, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 632613895 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 632613895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 16.aes_core_fi.64578216602358259668586266262395311321430839275026769577298483951542804480020
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011267812 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011267812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.73705760659739315004698393651262111480974013237075179505040195500224802392448
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10001795780 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001795780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 44.aes_core_fi.69570491184397549584356774746283306872559069652754515030431100773981541966956
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026221607 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x28d50c84) == 0x0
  UVM_INFO @ 10026221607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.40837346359165514627343006866089582217155754565278203014878390746027961119404
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014407137 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x39ec4784) == 0x0
  UVM_INFO @ 10014407137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.aes_csr_mem_rw_with_rand_reset.39581881264327915904081622285195525656391406221702357200679281824837566338190
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234565433 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 234565433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 13.aes_fi.43746646230677459086133108551759421338090054239724675520911442401079563862095
    Line 6280, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_fi/latest/run.log
```
  UVM_FATAL @  16462993 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  16462993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 19.aes_same_csr_outstanding.26567558802536481235971297164581574022811218361325543420718275187874399063492
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10077787818 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xfc359984) == 0x0
  UVM_INFO @ 10077787818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```