AES/UNMASKED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	69.262us	1	1	100.00
V1	smoke	aes_smoke	9.000s	87.556us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	124.252us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	94.672us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	709.790us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	133.490us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	72.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	94.672us	20	20	100.00
		aes_csr_aliasing	5.000s	133.490us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	87.556us	50	50	100.00
		aes_config_error	14.000s	114.841us	50	50	100.00
		aes_stress	19.000s	220.681us	50	50	100.00
V2	key_length	aes_smoke	9.000s	87.556us	50	50	100.00
		aes_config_error	14.000s	114.841us	50	50	100.00
		aes_stress	19.000s	220.681us	50	50	100.00
V2	back2back	aes_stress	19.000s	220.681us	50	50	100.00
		aes_b2b	18.000s	163.686us	50	50	100.00
V2	backpressure	aes_stress	19.000s	220.681us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	87.556us	50	50	100.00
		aes_config_error	14.000s	114.841us	50	50	100.00
		aes_stress	19.000s	220.681us	50	50	100.00
		aes_alert_reset	14.000s	78.069us	49	50	98.00
V2	failure_test	aes_man_cfg_err	13.000s	58.851us	50	50	100.00
		aes_config_error	14.000s	114.841us	50	50	100.00
		aes_alert_reset	14.000s	78.069us	49	50	98.00
V2	trigger_clear_test	aes_clear	14.000s	69.526us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	2.142ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	78.069us	49	50	98.00
V2	stress	aes_stress	19.000s	220.681us	50	50	100.00
V2	sideload	aes_stress	19.000s	220.681us	50	50	100.00
		aes_sideload	19.000s	74.654us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	148.065us	50	50	100.00
V2	stress_all	aes_stress_all	38.000s	7.734ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	55.077us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	879.554us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	879.554us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	124.252us	5	5	100.00
		aes_csr_rw	7.000s	94.672us	20	20	100.00
		aes_csr_aliasing	5.000s	133.490us	5	5	100.00
		aes_same_csr_outstanding	17.000s	10.575ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	124.252us	5	5	100.00
		aes_csr_rw	7.000s	94.672us	20	20	100.00
		aes_csr_aliasing	5.000s	133.490us	5	5	100.00
		aes_same_csr_outstanding	17.000s	10.575ms	19	20	95.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	14.000s	65.580us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	413.648us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	745.608us	5	5	100.00
		aes_tl_intg_err	13.000s	160.122us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	160.122us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	78.069us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	87.556us	50	50	100.00
		aes_stress	19.000s	220.681us	50	50	100.00
		aes_alert_reset	14.000s	78.069us	49	50	98.00
		aes_core_fi	6.550m	10.010ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	58.490us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	15.000s	73.004us	50	50	100.00
		aes_stress	19.000s	220.681us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	220.681us	50	50	100.00
		aes_sideload	19.000s	74.654us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	15.000s	73.004us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	15.000s	73.004us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	15.000s	73.004us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	15.000s	73.004us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	15.000s	73.004us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	220.681us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	220.681us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	123.223us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	123.223us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	65.627ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	123.223us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	78.069us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_ctr_fi	18.000s	61.234us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	123.223us	50	50	100.00
		aes_control_fi	52.000s	63.030ms	279	300	93.00
		aes_cipher_fi	50.000s	65.627ms	326	350	93.14
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.850m	15.460ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	10	76.92
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.43	94.18	98.77	93.68	97.72	93.33	98.66	95.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_cipher_fi has 13 failures.
  - 24.aes_cipher_fi.93429454822008802058777112202352121411042609589803333968992763869196087946144
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a4223ca6-56ee-48cd-92bc-d68ef4c533f8
```
  - 35.aes_cipher_fi.35231236248952007941079180418353579423899353758518182462844754418640942543850
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c4098224-6d1e-4d64-9574-5dc8f511ab3a
```
  - ... and 11 more failures.
- Test aes_control_fi has 10 failures.
  - 32.aes_control_fi.81772430542178489278305915702722018825014158133380786093392068786245391781370
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:45cdeca5-c1a4-4291-80f8-45475c6ba6d3
```
  - 44.aes_control_fi.20838153980983295604458106802726990167754321909099183871059640824360200455089
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:6dc9aa62-1b77-45dc-9760-9a698679c9b2
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 3.aes_control_fi.30431522559190645284720414800660256749465105691035233068515800006175031538163
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023716146 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023716146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_control_fi.115569265920611721872524273258533194403961848222508135815777026659267545276144
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10042744634 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042744634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 3.aes_cipher_fi.57276290407781244351565265731592224227020559957856719170040133512807168762860
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007360615 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007360615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_cipher_fi.101730342937410695671909671760301058417463339235264572971052156510966810468659
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014413066 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014413066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.92011922500605306475548733077394654992298042107689733665915942846291400533627
Line 717, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1334252723 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1334252723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.114268104645578310917196832267742697250927320970926316997273556049280724817677
Line 1524, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15459951070 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15459951070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.106607983757313714021003170967008439454314022266578539325149185896119520614330
Line 592, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 524680716 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 524680716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.10554274803979289488525008904624012431849461806999295839115270030090295869107
Line 1602, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 936878976 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 936878976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 3 failures:
- Test aes_core_fi has 3 failures.
  - 20.aes_core_fi.77772754892804464563359746022543779376936273389904360482669645024762356947523
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009791052 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xcfa77284) == 0x0
  UVM_INFO @ 10009791052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_core_fi.82342602592912330606067247824456292306621996690694694999839653178922265003159
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10042219512 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x88dd3e84) == 0x0
  UVM_INFO @ 10042219512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 53.aes_core_fi.32248901621717371677092129332962341989742729883172972262321658238218996470200
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016874390 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016874390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_core_fi.62036428298627633922835660860753883532152871129843706273035089191129610296526
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043138864 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043138864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 0.aes_same_csr_outstanding.38098068337941685254823509034006063547992501726674385564606639519830697608434
    Line 303, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10574577170 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x6db67184) == 0x0
  UVM_INFO @ 10574577170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 1.aes_core_fi.61067517710072284963849387178081603369349754669391244393895286215278314956210
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015133937 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015133937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 4.aes_stress_all.91335404740676327494953950113656200292274332186495497756333947143312832170507
    Line 4955, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all/latest/run.log
```
  UVM_ERROR @  67336135 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  67336135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

9.aes_alert_reset.101139458567023410927413002124320346896022436838378357635500043157734161444071
Line 4095, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 41787561 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 41747561 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 41787561 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 41747561 PS)
  UVM_ERROR @  41787561 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut