AES/UNMASKED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	53.276us	1	1	100.00
V1	smoke	aes_smoke	5.000s	104.647us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	54.057us	5	5	100.00
V1	csr_rw	aes_csr_rw	40.000s	10.036ms	18	20	90.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.173ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	270.148us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	102.489us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	40.000s	10.036ms	18	20	90.00
		aes_csr_aliasing	5.000s	270.148us	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	5.000s	104.647us	50	50	100.00
		aes_config_error	5.000s	142.862us	50	50	100.00
		aes_stress	6.000s	1.031ms	50	50	100.00
V2	key_length	aes_smoke	5.000s	104.647us	50	50	100.00
		aes_config_error	5.000s	142.862us	50	50	100.00
		aes_stress	6.000s	1.031ms	50	50	100.00
V2	back2back	aes_stress	6.000s	1.031ms	50	50	100.00
		aes_b2b	12.000s	700.278us	50	50	100.00
V2	backpressure	aes_stress	6.000s	1.031ms	50	50	100.00
V2	multi_message	aes_smoke	5.000s	104.647us	50	50	100.00
		aes_config_error	5.000s	142.862us	50	50	100.00
		aes_stress	6.000s	1.031ms	50	50	100.00
		aes_alert_reset	5.000s	200.968us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	53.925us	50	50	100.00
		aes_config_error	5.000s	142.862us	50	50	100.00
		aes_alert_reset	5.000s	200.968us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	210.657us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	346.329us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	200.968us	50	50	100.00
V2	stress	aes_stress	6.000s	1.031ms	50	50	100.00
V2	sideload	aes_stress	6.000s	1.031ms	50	50	100.00
		aes_sideload	6.000s	327.680us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	128.585us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	2.232ms	9	10	90.00
V2	alert_test	aes_alert_test	3.000s	58.174us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	312.603us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	312.603us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	54.057us	5	5	100.00
		aes_csr_rw	40.000s	10.036ms	18	20	90.00
		aes_csr_aliasing	5.000s	270.148us	5	5	100.00
		aes_same_csr_outstanding	4.000s	72.844us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	54.057us	5	5	100.00
		aes_csr_rw	40.000s	10.036ms	18	20	90.00
		aes_csr_aliasing	5.000s	270.148us	5	5	100.00
		aes_same_csr_outstanding	4.000s	72.844us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	13.000s	650.927us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	73.008us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	18.000s	3.850ms	5	5	100.00
		aes_tl_intg_err	5.000s	219.365us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	219.365us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	200.968us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	104.647us	50	50	100.00
		aes_stress	6.000s	1.031ms	50	50	100.00
		aes_alert_reset	5.000s	200.968us	50	50	100.00
		aes_core_fi	3.217m	10.022ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	94.304us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	145.487us	50	50	100.00
		aes_stress	6.000s	1.031ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	1.031ms	50	50	100.00
		aes_sideload	6.000s	327.680us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	145.487us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	145.487us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	145.487us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	145.487us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	145.487us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	1.031ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	1.031ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	308.460us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	308.460us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	16.442ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	308.460us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	200.968us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_ctr_fi	4.000s	71.275us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	308.460us	50	50	100.00
		aes_control_fi	52.000s	47.749ms	275	300	91.67
		aes_cipher_fi	44.000s	16.442ms	329	350	94.00
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.683m	47.906ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.44	94.22	98.75	93.57	97.64	91.11	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 15 failures.
  - 10.aes_control_fi.23971137273845636488896044626176585648200932353773973419772180102324669499802
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:c996b85b-69f2-4947-a746-a66adb9ea3eb
```
  - 14.aes_control_fi.54483110789257315431263001133537753925423560362634454477482027801980029669630
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job ID: smart:9e1506db-34d6-4c0c-be8f-0addd255f84c
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 9 failures.
  - 75.aes_cipher_fi.52269650307634717758515975393408097262904603847694905889354113243457288680255
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6cbacb58-0a04-4c68-9b83-425eb2a9568d
```
  - 123.aes_cipher_fi.91294143699878187793255752046949539555451158051144188548781916889183010426222
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/123.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5ee04215-fe3d-44c0-a59a-4d4ef5ab4526
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 10.aes_cipher_fi.52682231086715983963417179762627282851449151456469676644368348462901719215448
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004101235 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004101235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 88.aes_cipher_fi.36746180049440020095565839514516460770486720337373751094947826740368768092832
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/88.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005979242 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005979242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 11.aes_control_fi.35080350596447109287158055348919087389875596664860119359702413772059266136819
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009560530 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009560530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_control_fi.49980733171978176037327004683188681418026436789354248707412000748893878978527
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003752907 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003752907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.23298019976382462319605754344506893232905666677427393981025282260196834015973
Line 646, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47906368695 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 47906368695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.36734664367036832013821818993711822021717109026637398937454264064432145505652
Line 1597, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2460446997 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2460446997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.99607724100707774627803171934630377781247551079656815422469857663968847511021
Line 984, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1000601535 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1000601535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.71762229330294056415229156860953993939535725338659716896313853635469342348227
Line 1021, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 234336008 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 234336008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_csr_rw has 2 failures.
  - 6.aes_csr_rw.69473177640807249141501483743853496740880482268386827496295486959928493340477
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10063993577 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xf6e31184) == 0x0
  UVM_INFO @ 10063993577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_csr_rw.27663826178783545865736628719456021747068636420320139595851472244222506392236
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10035569054 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x90889684) == 0x0
  UVM_INFO @ 10035569054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 32.aes_core_fi.32763491719926343658988151849635633402404899483523194067862319149265240172824
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010963780 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010963780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_core_fi.67808086521873687425837618456021333210371484627698341168289096845474170420458
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006425503 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006425503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 2.aes_stress_all.11629496261164798204273322689230704772945194483716802794188786482430864422638
    Line 48633, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 849989013 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 849939013 PS)
  UVM_ERROR @ 849989013 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 849989013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 5.aes_core_fi.53893021227928653673494573439553771432053608312683435290604385669132136733448
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022034710 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb694ed84) == 0x0
  UVM_INFO @ 10022034710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 20.aes_core_fi.32905832902452215992663708128060449551989107026342801715462522023208520533805
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013286482 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013286482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```