AES/UNMASKED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	80.709us	1	1	100.00
V1	smoke	aes_smoke	9.000s	104.372us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	78.565us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	61.379us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.347ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	176.870us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	148.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	61.379us	20	20	100.00
		aes_csr_aliasing	5.000s	176.870us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	104.372us	50	50	100.00
		aes_config_error	13.000s	113.855us	50	50	100.00
		aes_stress	10.000s	308.909us	50	50	100.00
V2	key_length	aes_smoke	9.000s	104.372us	50	50	100.00
		aes_config_error	13.000s	113.855us	50	50	100.00
		aes_stress	10.000s	308.909us	50	50	100.00
V2	back2back	aes_stress	10.000s	308.909us	50	50	100.00
		aes_b2b	13.000s	117.489us	50	50	100.00
V2	backpressure	aes_stress	10.000s	308.909us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	104.372us	50	50	100.00
		aes_config_error	13.000s	113.855us	50	50	100.00
		aes_stress	10.000s	308.909us	50	50	100.00
		aes_alert_reset	10.000s	349.171us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	71.546us	50	50	100.00
		aes_config_error	13.000s	113.855us	50	50	100.00
		aes_alert_reset	10.000s	349.171us	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	115.454us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	106.342us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	349.171us	50	50	100.00
V2	stress	aes_stress	10.000s	308.909us	50	50	100.00
V2	sideload	aes_stress	10.000s	308.909us	50	50	100.00
		aes_sideload	11.000s	74.248us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	65.980us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	987.078us	9	10	90.00
V2	alert_test	aes_alert_test	12.000s	111.350us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	1.097ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	1.097ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	78.565us	5	5	100.00
		aes_csr_rw	3.000s	61.379us	20	20	100.00
		aes_csr_aliasing	5.000s	176.870us	5	5	100.00
		aes_same_csr_outstanding	1.617m	10.031ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	78.565us	5	5	100.00
		aes_csr_rw	3.000s	61.379us	20	20	100.00
		aes_csr_aliasing	5.000s	176.870us	5	5	100.00
		aes_same_csr_outstanding	1.617m	10.031ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	14.000s	67.411us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.150m	10.020ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	8.000s	2.927ms	5	5	100.00
		aes_tl_intg_err	6.000s	807.574us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	807.574us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	349.171us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	104.372us	50	50	100.00
		aes_stress	10.000s	308.909us	50	50	100.00
		aes_alert_reset	10.000s	349.171us	50	50	100.00
		aes_core_fi	4.267m	10.016ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	93.054us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	93.304us	50	50	100.00
		aes_stress	10.000s	308.909us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	308.909us	50	50	100.00
		aes_sideload	11.000s	74.248us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	93.304us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	93.304us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	93.304us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	93.304us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	93.304us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	308.909us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	308.909us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	167.902us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	167.902us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	16.443ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	167.902us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	349.171us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_ctr_fi	13.000s	59.553us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	167.902us	49	50	98.00
		aes_control_fi	51.000s	22.540ms	276	300	92.00
		aes_cipher_fi	51.000s	16.443ms	322	350	92.00
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	11.250m	27.371ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1533	1602	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.48	94.31	98.81	93.63	97.72	93.33	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_cipher_fi has 17 failures.
  - 13.aes_cipher_fi.53714303331993040779339893426771528947315462611508217166662062290857397047
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6a0ce86f-a966-4bcc-be20-0eb097ece370
```
  - 19.aes_cipher_fi.89141359400387309456330903617669643057315472992584137665942509023172017804781
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c3b700e2-3127-4ab3-b6e3-a78bccd334f2
```
  - ... and 15 more failures.
- Test aes_control_fi has 15 failures.
  - 19.aes_control_fi.88517224519498310067399035756022570906254792049064658301493880947777270242674
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:9ba9e828-77a4-4773-9516-c3b21aa3cc3a
```
  - 52.aes_control_fi.47947052170350976322251895637554337021718580492414588514373662799044499671919
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:1578ab04-6ba7-493f-935d-2715a47c947a
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 0.aes_cipher_fi.14786422938520203108420539363301189537750848829319987417600470205909233891133
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003408605 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003408605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_cipher_fi.21606862979272876434954831578238582084275340231083137907237119794843994895386
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018276240 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018276240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.53185368704988059434730700634894183144469380905121640982536990403144044474450
Line 513, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 521808908 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 521808908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.6310347108122950659976786990242243964844715983748306341814227621853460744189
Line 1404, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3271622592 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3271622592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 43.aes_control_fi.36694350016726200079076731734916085696427222358866376442143845753004997324576
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004105552 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004105552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_control_fi.43742830851194049690791207744313127036317357511431553819606547324923174589310
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027114136 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027114136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 1.aes_same_csr_outstanding.101966403015908754748599752589236557964996165718665373304674597668215061821845
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10031429133 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xd1e97884) == 0x0
  UVM_INFO @ 10031429133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 8.aes_shadow_reg_errors_with_csr_rw.96728257851576664937861990014961871320349405247923710608144236982131534825394
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10020242305 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x87d4af84) == 0x0
  UVM_INFO @ 10020242305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 22.aes_core_fi.17013272233265372805076858670445636305473884626179748927614965985304615074629
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015874250 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x8c05ad84) == 0x0
  UVM_INFO @ 10015874250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_core_fi.9425743953544878921105261065072819445102954381503576883888951589029792527031
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10029466668 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd4610884) == 0x0
  UVM_INFO @ 10029466668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 2.aes_core_fi.16596699421636130592576898041660959416160111733503348894271030946650542621662
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10027273262 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027273262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

5.aes_stress_all.1324714193971266398556747939216652758319950415261137825418016463806546218812
Line 53250, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 3133606749 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 3133463892 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 3133606749 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 3133463892 PS)
  UVM_ERROR @ 3133606749 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 33.aes_fi.93283295078138980031614723745638460520164309084618309440424951662950489616356
    Line 968, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 12798183 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 12758183 PS)
  UVM_ERROR @  12798183 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  12798183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```