AES/UNMASKED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	95.550us	1	1	100.00
V1	smoke	aes_smoke	12.000s	86.419us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	85.568us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	66.447us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.216ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	165.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	107.330us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	66.447us	20	20	100.00
		aes_csr_aliasing	5.000s	165.169us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	86.419us	50	50	100.00
		aes_config_error	13.000s	283.176us	50	50	100.00
		aes_stress	16.000s	160.124us	50	50	100.00
V2	key_length	aes_smoke	12.000s	86.419us	50	50	100.00
		aes_config_error	13.000s	283.176us	50	50	100.00
		aes_stress	16.000s	160.124us	50	50	100.00
V2	back2back	aes_stress	16.000s	160.124us	50	50	100.00
		aes_b2b	16.000s	389.615us	50	50	100.00
V2	backpressure	aes_stress	16.000s	160.124us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	86.419us	50	50	100.00
		aes_config_error	13.000s	283.176us	50	50	100.00
		aes_stress	16.000s	160.124us	50	50	100.00
		aes_alert_reset	19.000s	168.577us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	78.359us	50	50	100.00
		aes_config_error	13.000s	283.176us	50	50	100.00
		aes_alert_reset	19.000s	168.577us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	152.269us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	228.928us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	168.577us	50	50	100.00
V2	stress	aes_stress	16.000s	160.124us	50	50	100.00
V2	sideload	aes_stress	16.000s	160.124us	50	50	100.00
		aes_sideload	15.000s	93.613us	50	50	100.00
V2	deinitialization	aes_deinit	23.000s	87.436us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	546.952us	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	133.116us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	127.478us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	127.478us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	85.568us	5	5	100.00
		aes_csr_rw	4.000s	66.447us	20	20	100.00
		aes_csr_aliasing	5.000s	165.169us	5	5	100.00
		aes_same_csr_outstanding	8.000s	109.475us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	85.568us	5	5	100.00
		aes_csr_rw	4.000s	66.447us	20	20	100.00
		aes_csr_aliasing	5.000s	165.169us	5	5	100.00
		aes_same_csr_outstanding	8.000s	109.475us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	60.112us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	309.326us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	361.611us	5	5	100.00
		aes_tl_intg_err	7.000s	481.279us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	481.279us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	168.577us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	86.419us	50	50	100.00
		aes_stress	16.000s	160.124us	50	50	100.00
		aes_alert_reset	19.000s	168.577us	50	50	100.00
		aes_core_fi	1.800m	10.038ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	90.528us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	110.312us	50	50	100.00
		aes_stress	16.000s	160.124us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	160.124us	50	50	100.00
		aes_sideload	15.000s	93.613us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	110.312us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	110.312us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	110.312us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	110.312us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	110.312us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	160.124us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	160.124us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	256.914us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	256.914us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	19.481ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	256.914us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	168.577us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_ctr_fi	19.000s	124.430us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	256.914us	50	50	100.00
		aes_control_fi	51.000s	19.970ms	273	300	91.00
		aes_cipher_fi	47.000s	19.481ms	323	350	92.29
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.617m	862.580ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.55	94.48	98.81	93.68	97.72	93.33	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_cipher_fi has 15 failures.
  - 21.aes_cipher_fi.25517657753450456028437391040933326345704163798848492951875612064268383389178
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4c79962f-561c-481f-a66d-bc03fd4c4f57
```
  - 69.aes_cipher_fi.79079669921547237166240933498497673966017168331213280776330378472198448902115
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e83e189a-6d60-4fb9-9909-545b77f7b4fa
```
  - ... and 13 more failures.
- Test aes_control_fi has 19 failures.
  - 46.aes_control_fi.2775923157073660380018102360845357740902172413070746596894841021415895627947
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job ID: smart:1cbdbfc2-101a-4872-bfa0-b1eebdc6bdee
```
  - 53.aes_control_fi.21263454605488862023702506873047914342755649358640377764724952967096807036296
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  Job ID: smart:52988b05-746e-4677-960a-9d63f4fa734e
```
  - ... and 17 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 38.aes_cipher_fi.15720309968801212908493917192155364691425409595838068811837370748231512209144
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008260383 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008260383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 66.aes_cipher_fi.18340198227753980901321211526813355576635447271559017190051780527952393547641
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007641741 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007641741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 36.aes_control_fi.82922669475509185411425429819583751875959936671278146799708056401007437031631
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10001993790 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001993790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_control_fi.97039498885334446186106826578863917123944692203000375610855790073992666803043
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011060817 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011060817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.45011597980639736237090611156616583315954134113089388393671825270791949660979
Line 1842, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 470556873 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 470556873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.86628232634247134825595099628587138651238548586264774295892727712817776138144
Line 1261, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 862580167594 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 862580167594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.25141393914281447425547681123555501557963120414730667011414306153503788075055
Line 1528, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 783179185 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 783179185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.11634333926416146436715542022002106070604247089010322827761976767866749772492
Line 1076, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11805295662 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 11805295662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 8.aes_core_fi.91220489978068262521739582666039930517635157653912136474101445607993000480384
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022497179 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022497179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_core_fi.58311765716276288206226316541154368535656032513206415227975612640249360286119
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006732783 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006732783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.84351526114026766623594154440144548486031059034003695270443361405259931984308
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031955217 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x35f40084) == 0x0
  UVM_INFO @ 10031955217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_core_fi.100740426597574897883841064992500774804405933334296506293928784655452225938712
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038432186 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf4904484) == 0x0
  UVM_INFO @ 10038432186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.114254879278740294537875101732860978822705102480018216707918233707184995651921
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014243197 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014243197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```