AES/UNMASKED Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	200.502us	1	1	100.00
V1	smoke	aes_smoke	4.000s	59.692us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	57.481us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.317m	10.016ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.895ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	606.987us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	137.231us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.317m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	606.987us	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	4.000s	59.692us	50	50	100.00
		aes_config_error	6.000s	262.870us	50	50	100.00
		aes_stress	9.000s	390.246us	50	50	100.00
V2	key_length	aes_smoke	4.000s	59.692us	50	50	100.00
		aes_config_error	6.000s	262.870us	50	50	100.00
		aes_stress	9.000s	390.246us	50	50	100.00
V2	back2back	aes_stress	9.000s	390.246us	50	50	100.00
		aes_b2b	11.000s	1.198ms	50	50	100.00
V2	backpressure	aes_stress	9.000s	390.246us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	59.692us	50	50	100.00
		aes_config_error	6.000s	262.870us	50	50	100.00
		aes_stress	9.000s	390.246us	50	50	100.00
		aes_alert_reset	5.000s	77.402us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	101.693us	50	50	100.00
		aes_config_error	6.000s	262.870us	50	50	100.00
		aes_alert_reset	5.000s	77.402us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	1.128ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	3.903ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	77.402us	50	50	100.00
V2	stress	aes_stress	9.000s	390.246us	50	50	100.00
V2	sideload	aes_stress	9.000s	390.246us	50	50	100.00
		aes_sideload	4.000s	191.321us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	125.669us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	659.255us	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	61.650us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	605.642us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	605.642us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	57.481us	5	5	100.00
		aes_csr_rw	1.317m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	606.987us	5	5	100.00
		aes_same_csr_outstanding	4.000s	68.768us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	57.481us	5	5	100.00
		aes_csr_rw	1.317m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	606.987us	5	5	100.00
		aes_same_csr_outstanding	4.000s	68.768us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	5.000s	498.720us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	148.808us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	530.117us	5	5	100.00
		aes_tl_intg_err	6.000s	455.889us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	455.889us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	77.402us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	59.692us	50	50	100.00
		aes_stress	9.000s	390.246us	50	50	100.00
		aes_alert_reset	5.000s	77.402us	50	50	100.00
		aes_core_fi	6.633m	10.011ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	61.625us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	169.999us	50	50	100.00
		aes_stress	9.000s	390.246us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	390.246us	50	50	100.00
		aes_sideload	4.000s	191.321us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	169.999us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	169.999us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	169.999us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	169.999us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	169.999us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	390.246us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	390.246us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	855.352us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	855.352us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	15.785ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	855.352us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	77.402us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_ctr_fi	5.000s	157.661us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	855.352us	49	50	98.00
		aes_control_fi	51.000s	10.003ms	280	300	93.33
		aes_cipher_fi	47.000s	15.785ms	327	350	93.43
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	909.103us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.54	94.43	98.79	93.65	97.72	91.85	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 13 failures.
  - 11.aes_control_fi.37552711400146182533688395348465846914494072524427623024984989158385389317671
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job ID: smart:60fb05b2-abe5-4680-a208-96b1fb47a956
```
  - 39.aes_control_fi.39692531104520361031744906317927260142802776194252926358963235781432383730185
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:178ea0dc-d446-4979-924a-a80e21ef6704
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 15 failures.
  - 12.aes_cipher_fi.9123093476440753485712607009190712010470725654164662308195496407068490159958
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d2d5eea1-f718-44a3-8450-6061b8a8a52e
```
  - 14.aes_cipher_fi.16854981580774275044645864362029351754754783828272259634314265179010631406189
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ac13f661-aa46-4905-bc23-5957cfeb3a57
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 4.aes_cipher_fi.63728970358032476419697191770481287862236381211758494968027629662570400286873
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021509743 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021509743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_cipher_fi.86986910547341939564841677904826843181136710503848164796020027971417711393213
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013718633 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013718633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.58543161520103709603109678554894819066979904235457930389411043411256690283375
Line 1636, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 856518180 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 856518180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.78043165720948888717239341707482815395724637953414511448709979388627139536372
Line 938, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 418721820 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 418721820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 161.aes_control_fi.5374736665260378728602673791950067111983566449552334196493708492931650650390
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/161.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013929539 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013929539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 187.aes_control_fi.31796737306322659549907508427752869468357893106850733666036538213091085544797
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/187.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007707488 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007707488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.49101739744989685007773698147584372736240124837785846484515311341290896519317
Line 1174, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3263380561 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3263380561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.89543365132184490984445566986646458361316275819994440681229073339415568155054
Line 1663, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 909103370 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 909103370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 29.aes_core_fi.85922513408641727231260566262882573750174891571074361421958554900647407496247
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009334998 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009334998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_core_fi.70138726893077901727854522792331561385897530980827554042239918544009360891572
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006413006 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006413006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.aes_csr_mem_rw_with_rand_reset.14111195975560573155595639838675237797965810307726026874025352757185581081199
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137231065 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137231065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.14854170449598232603648144734350217981711895792314371305929290998428854070241
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  42161885 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  42161885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 11.aes_csr_rw.88201618665530563024962576432945580089002215431323287171496946788142181515893
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10016489335 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x87d67e84) == 0x0
  UVM_INFO @ 10016489335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 22.aes_fi.63335360717135034380060421497858047616230872982123614267540351682582786143907
    Line 5705, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_fi/latest/run.log
```
  UVM_FATAL @  62136584 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  62136584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 41.aes_core_fi.52699995131068574092944326683612593447420233636912323673894938993356462365330
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010580042 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x24439484) == 0x0
  UVM_INFO @ 10010580042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```