AES/UNMASKED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	84.465us	1	1	100.00
V1	smoke	aes_smoke	6.000s	307.690us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	228.334us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	95.338us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	702.140us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	591.667us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	65.025us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	95.338us	20	20	100.00
		aes_csr_aliasing	7.000s	591.667us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	307.690us	50	50	100.00
		aes_config_error	8.000s	66.988us	50	50	100.00
		aes_stress	6.000s	143.281us	50	50	100.00
V2	key_length	aes_smoke	6.000s	307.690us	50	50	100.00
		aes_config_error	8.000s	66.988us	50	50	100.00
		aes_stress	6.000s	143.281us	50	50	100.00
V2	back2back	aes_stress	6.000s	143.281us	50	50	100.00
		aes_b2b	13.000s	209.244us	50	50	100.00
V2	backpressure	aes_stress	6.000s	143.281us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	307.690us	50	50	100.00
		aes_config_error	8.000s	66.988us	50	50	100.00
		aes_stress	6.000s	143.281us	50	50	100.00
		aes_alert_reset	8.000s	85.702us	49	50	98.00
V2	failure_test	aes_man_cfg_err	10.000s	136.388us	50	50	100.00
		aes_config_error	8.000s	66.988us	50	50	100.00
		aes_alert_reset	8.000s	85.702us	49	50	98.00
V2	trigger_clear_test	aes_clear	9.000s	73.166us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	970.383us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	85.702us	49	50	98.00
V2	stress	aes_stress	6.000s	143.281us	50	50	100.00
V2	sideload	aes_stress	6.000s	143.281us	50	50	100.00
		aes_sideload	6.000s	602.567us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	101.732us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	1.556ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	55.087us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	250.331us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	250.331us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	228.334us	5	5	100.00
		aes_csr_rw	8.000s	95.338us	20	20	100.00
		aes_csr_aliasing	7.000s	591.667us	5	5	100.00
		aes_same_csr_outstanding	1.083m	10.092ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	228.334us	5	5	100.00
		aes_csr_rw	8.000s	95.338us	20	20	100.00
		aes_csr_aliasing	7.000s	591.667us	5	5	100.00
		aes_same_csr_outstanding	1.083m	10.092ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	9.000s	148.721us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	251.855us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.977ms	5	5	100.00
		aes_tl_intg_err	9.000s	181.191us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	181.191us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	85.702us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	307.690us	50	50	100.00
		aes_stress	6.000s	143.281us	50	50	100.00
		aes_alert_reset	8.000s	85.702us	49	50	98.00
		aes_core_fi	1.667m	10.031ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	80.381us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	58.974us	50	50	100.00
		aes_stress	6.000s	143.281us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	143.281us	50	50	100.00
		aes_sideload	6.000s	602.567us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	58.974us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	58.974us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	58.974us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	58.974us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	58.974us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	143.281us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	143.281us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	70.176us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	70.176us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.002ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	70.176us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	85.702us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_ctr_fi	8.000s	109.051us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	70.176us	50	50	100.00
		aes_control_fi	42.000s	63.018ms	278	300	92.67
		aes_cipher_fi	50.000s	10.002ms	318	350	90.86
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.850m	33.211ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1533	1602	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.50	94.35	98.81	93.65	97.72	93.33	98.66	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test aes_control_fi has 11 failures.
  - 17.aes_control_fi.33926695796911806439369662898793687297789205692094929870937346543927136564712
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:8cb61ba9-fcb1-48b5-a9c1-e9218136cde1
```
  - 30.aes_control_fi.58147665074921751137048653326083346887864180050820078548186221379147580702202
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:9cb17de5-f257-4efa-b6d8-dfa2453fbcda
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 24 failures.
  - 18.aes_cipher_fi.68817060918604844229479334593895015386741734942682054508999345315401310560628
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:89c63468-f5f6-49f8-9ffc-fc57f06df850
```
  - 44.aes_cipher_fi.18907971883800379454136973119473511599733553029444713116876064797731467591405
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ef554ed0-3357-4223-8d4e-45c7cea8d0b7
```
  - ... and 22 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 32.aes_control_fi.95388650804155017382512084773896678336230300598087438291286838740560649134522
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017605961 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017605961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_control_fi.105993404861683617196954743839856719947989322181223870194268537051450920490391
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002963548 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002963548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.97406076871932759544504960477680384391567523339575700976464663939832524609816
Line 1416, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7571346879 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7571346879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.39357399860812791922361901640032224751426734990807856307276981221613651617062
Line 1117, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 565905077 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 565905077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 17.aes_cipher_fi.13067687225604447868257153006830891670896407600771802239888632639807878498367
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004859637 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004859637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 86.aes_cipher_fi.11757786449973085026732050568557812030273652572984923034361937988661069214158
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005492711 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005492711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.91916010449420156397144415111410678533466103715543147045840882672137997567007
Line 831, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 375669972 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 375669972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.77887720516402950079167999120479334632659365171141787248114640961628338388962
Line 1415, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1432904002 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1432904002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 20.aes_core_fi.60646091953637371295579514154131646082456255939514927386729296750476196555628
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004059405 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004059405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_core_fi.25561743485274184953941311544266812284701451885178801821496586936979454529997
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006229618 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006229618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 10.aes_alert_reset.67520508734583748206955698991314159926809182031620367437545318057164449239827
    Line 3401, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 36165086 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 36123419 PS)
  UVM_ERROR @  36165086 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  36165086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 15.aes_same_csr_outstanding.41291540003910323360157975192186653326032199326825005950382589958610867545912
    Line 297, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10092105102 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x69938a84) == 0x0
  UVM_INFO @ 10092105102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 33.aes_core_fi.36454451307800900432501814347939780711177596827415273523498043157982124922441
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030574925 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x404f1184) == 0x0
  UVM_INFO @ 10030574925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```