AES/UNMASKED Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	100.791us	1	1	100.00
V1	smoke	aes_smoke	12.000s	59.024us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	63.543us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.333m	10.021ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.052ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	95.900us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	71.528us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.333m	10.021ms	19	20	95.00
		aes_csr_aliasing	5.000s	95.900us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	12.000s	59.024us	50	50	100.00
		aes_config_error	12.000s	260.915us	50	50	100.00
		aes_stress	15.000s	167.642us	50	50	100.00
V2	key_length	aes_smoke	12.000s	59.024us	50	50	100.00
		aes_config_error	12.000s	260.915us	50	50	100.00
		aes_stress	15.000s	167.642us	50	50	100.00
V2	back2back	aes_stress	15.000s	167.642us	50	50	100.00
		aes_b2b	23.000s	168.702us	50	50	100.00
V2	backpressure	aes_stress	15.000s	167.642us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	59.024us	50	50	100.00
		aes_config_error	12.000s	260.915us	50	50	100.00
		aes_stress	15.000s	167.642us	50	50	100.00
		aes_alert_reset	13.000s	296.709us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	117.005us	50	50	100.00
		aes_config_error	12.000s	260.915us	50	50	100.00
		aes_alert_reset	13.000s	296.709us	49	50	98.00
V2	trigger_clear_test	aes_clear	15.000s	209.715us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	114.807us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	296.709us	49	50	98.00
V2	stress	aes_stress	15.000s	167.642us	50	50	100.00
V2	sideload	aes_stress	15.000s	167.642us	50	50	100.00
		aes_sideload	18.000s	88.421us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	147.609us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	895.270us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	59.103us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	247.730us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	247.730us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	63.543us	5	5	100.00
		aes_csr_rw	1.333m	10.021ms	19	20	95.00
		aes_csr_aliasing	5.000s	95.900us	5	5	100.00
		aes_same_csr_outstanding	13.000s	59.814us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	63.543us	5	5	100.00
		aes_csr_rw	1.333m	10.021ms	19	20	95.00
		aes_csr_aliasing	5.000s	95.900us	5	5	100.00
		aes_same_csr_outstanding	13.000s	59.814us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	14.000s	89.703us	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	168.527us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	930.617us	5	5	100.00
		aes_tl_intg_err	9.000s	2.092ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	2.092ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	296.709us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	59.024us	50	50	100.00
		aes_stress	15.000s	167.642us	50	50	100.00
		aes_alert_reset	13.000s	296.709us	49	50	98.00
		aes_core_fi	25.000s	10.006ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	71.689us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	15.000s	193.357us	50	50	100.00
		aes_stress	15.000s	167.642us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	167.642us	50	50	100.00
		aes_sideload	18.000s	88.421us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	15.000s	193.357us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	15.000s	193.357us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	15.000s	193.357us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	15.000s	193.357us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	15.000s	193.357us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	167.642us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	167.642us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	111.201us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	111.201us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	32.838ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	111.201us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	296.709us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_ctr_fi	10.000s	58.405us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	111.201us	50	50	100.00
		aes_control_fi	49.000s	16.440ms	276	300	92.00
		aes_cipher_fi	50.000s	32.838ms	329	350	94.00
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.650m	13.171ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	11	84.62
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.28	97.57	94.52	98.81	93.91	97.72	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_control_fi has 19 failures.
  - 2.aes_control_fi.12746976233842634281342993379946811212588787867758792526519367606667155036154
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job ID: smart:9116d00d-4035-402d-8078-2768376520f4
```
  - 4.aes_control_fi.82115591322291479886112725639226403746788920673386365806082482230788526680320
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:1bb6e4c0-d9f5-4d36-a28e-3f2bda26716c
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 13 failures.
  - 14.aes_cipher_fi.104804301802769740724385832915568084256489728312063898975293873160186376601051
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b94e0442-4b3c-4a82-a6e3-178e8a356274
```
  - 82.aes_cipher_fi.50340668294341693803179032259755690051773793752660729257055221040340159046873
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/82.aes_cipher_fi/latest/run.log
```
  Job ID: smart:79520994-7a12-424e-b92b-73fe85b31f26
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 7.aes_cipher_fi.25754204049688835958984831830643016409954150565600967105918086195215870270212
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003285876 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003285876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.22734144759710547668649642490075078593646719738291418583075789203389477738577
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008232948 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008232948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.83395369741386847346217944743541271689907884371762990108170468434429457131931
Line 711, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 702478523 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 702478523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.32588057301166032034019641920291300175152671279031460832014821400172804324935
Line 1332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13171178005 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 13171178005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 108.aes_control_fi.27152136703264784196996059748654350908106069188940965532645089685892947166976
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/108.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002943081 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002943081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 118.aes_control_fi.80723721775394971843011775144475154012997725885363881621456515811553350092850
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/118.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014059892 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014059892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.52954410153370091973717407411270353272174811648389492394513742028909611449127
Line 1436, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 996318374 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 996318374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.76440928916834845909631825490285514240676990663367719828231349193980501353972
Line 1627, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 944442590 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 944442590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 41.aes_core_fi.51053160105126712003519903129985594760704401998397202895016279178485075706879
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10034660726 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034660726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.aes_core_fi.71021032021783919990266682429515776129848192568725202550919392959002055644009
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005856508 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005856508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 13.aes_csr_rw.3511034396915386662156380756274032206567129767037201760268682555900089880223
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10021374462 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x3f33e284) == 0x0
  UVM_INFO @ 10021374462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 23.aes_core_fi.97117913597932246381063957172694495396275146545735904815688417265326189959003
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031653152 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031653152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 31.aes_alert_reset.90422171631353693778570401655105225566674055131943736617416785859861449651978
    Line 566, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9716424 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9695591 PS)
  UVM_ERROR @   9716424 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9716424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1 failures:
- Test aes_clear has 1 failures.
  - 42.aes_clear.14916743185712370679569845466669781803776194651201001442393637020729488772361
    Line 6082, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_clear/latest/run.log
```
  UVM_FATAL @ 165854025 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
       ----| Expected:           3
       ----| Seen:               4
       ----| Expected corrupted: 0
```