AES/UNMASKED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.919us	1	1	100.00
V1	smoke	aes_smoke	9.000s	602.281us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.830us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.117m	10.012ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	541.251us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	210.929us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	104.249us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.117m	10.012ms	19	20	95.00
		aes_csr_aliasing	5.000s	210.929us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	9.000s	602.281us	50	50	100.00
		aes_config_error	22.000s	58.532us	50	50	100.00
		aes_stress	14.000s	84.446us	50	50	100.00
V2	key_length	aes_smoke	9.000s	602.281us	50	50	100.00
		aes_config_error	22.000s	58.532us	50	50	100.00
		aes_stress	14.000s	84.446us	50	50	100.00
V2	back2back	aes_stress	14.000s	84.446us	50	50	100.00
		aes_b2b	15.000s	117.810us	50	50	100.00
V2	backpressure	aes_stress	14.000s	84.446us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	602.281us	50	50	100.00
		aes_config_error	22.000s	58.532us	50	50	100.00
		aes_stress	14.000s	84.446us	50	50	100.00
		aes_alert_reset	9.000s	205.918us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	68.893us	50	50	100.00
		aes_config_error	22.000s	58.532us	50	50	100.00
		aes_alert_reset	9.000s	205.918us	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	85.552us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	170.636us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	205.918us	50	50	100.00
V2	stress	aes_stress	14.000s	84.446us	50	50	100.00
V2	sideload	aes_stress	14.000s	84.446us	50	50	100.00
		aes_sideload	9.000s	59.975us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	94.341us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	1.746ms	10	10	100.00
V2	alert_test	aes_alert_test	15.000s	58.813us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	185.839us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	185.839us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.830us	5	5	100.00
		aes_csr_rw	1.117m	10.012ms	19	20	95.00
		aes_csr_aliasing	5.000s	210.929us	5	5	100.00
		aes_same_csr_outstanding	4.000s	101.746us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.830us	5	5	100.00
		aes_csr_rw	1.117m	10.012ms	19	20	95.00
		aes_csr_aliasing	5.000s	210.929us	5	5	100.00
		aes_same_csr_outstanding	4.000s	101.746us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	16.000s	1.563ms	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	163.563us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	348.405us	5	5	100.00
		aes_tl_intg_err	8.000s	113.634us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	113.634us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	205.918us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	602.281us	50	50	100.00
		aes_stress	14.000s	84.446us	50	50	100.00
		aes_alert_reset	9.000s	205.918us	50	50	100.00
		aes_core_fi	1.550m	10.048ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	145.612us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	59.399us	50	50	100.00
		aes_stress	14.000s	84.446us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	84.446us	50	50	100.00
		aes_sideload	9.000s	59.975us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	59.399us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	59.399us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	59.399us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	59.399us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	59.399us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	84.446us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	84.446us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	72.630us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	72.630us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	56.278ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	72.630us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	205.918us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	63.777us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	72.630us	50	50	100.00
		aes_control_fi	42.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	56.278ms	326	350	93.14
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	31.000s	1.148ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.46	94.26	98.75	93.80	97.72	91.11	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 17 failures.
  - 5.aes_control_fi.66624491343032893025021697763800234818040654032351564390758962867095944450595
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:bd9e6d6a-bf12-4129-9ea4-4eff2dd12951
```
  - 8.aes_control_fi.76435205822431015887803384289410690035418876083395538437754744234182067972423
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:1e808c37-cfcb-4f11-bbe9-f161d675aeb1
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 12 failures.
  - 8.aes_cipher_fi.88421853882138665239433592505656218455312240897791646227115438157485535135259
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5976ad1a-a620-4183-b077-fa4e501c7660
```
  - 21.aes_cipher_fi.42288130006289787541815177421146088641901946146877031856440889392257794593134
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ca17b18b-cd5a-410c-b865-f711ff091c41
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 27.aes_cipher_fi.75918767882012785390232598818726257047399817486894944742462235776093056607669
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004040888 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004040888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.aes_cipher_fi.64764633258558244103598126918122624195202105762928304992715698983771501441063
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/94.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009514665 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009514665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.114036502892879206047872503497842401787989218012831055334869390089939609381484
Line 1779, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4063678310 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4063678310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.101167878296949305891463322269411849088888346646379421299912052054536689293988
Line 1832, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 872483946 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 872483946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 204.aes_control_fi.46854110609239366478371570608953630787604478310228707907625649380752390238466
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/204.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026758567 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026758567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 217.aes_control_fi.11563218607220836124388227706652194081458303599048429808414444787226561787168
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/217.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008207189 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008207189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.58013342921673972646664362687459188996310216990120247933996600865813600268393
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022241601 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022241601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_core_fi.33212235019623139484612242741463089040571451109197043629357270187036278362731
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003321909 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003321909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.105323334964000203776044872998103732428117999129584101119851046959324862087868
    Line 1046, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3038078030 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3038078030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.55023998018282457426846574174601568596491918169905214290947280719579447206169
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  17705159 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  17705159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 8.aes_csr_rw.3358141879158777219743399707324990450181299716372175976034119517687189375366
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10011924887 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xd8f94484) == 0x0
  UVM_INFO @ 10011924887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.4059254080715943427013986957689142209110474057727563517918665502970938736175
    Line 1056, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 845550026 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 845516693 PS)
  UVM_ERROR @ 845550026 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 845550026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 12.aes_core_fi.7444489215749976466996919793297146051218965060238169912853409065438199319200
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10047745432 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd5993684) == 0x0
  UVM_INFO @ 10047745432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```