AES/UNMASKED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	172.888us	1	1	100.00
V1	smoke	aes_smoke	9.000s	143.070us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	61.692us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	65.159us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	9.266ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	1.730ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	733.096us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	65.159us	20	20	100.00
		aes_csr_aliasing	6.000s	1.730ms	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	9.000s	143.070us	50	50	100.00
		aes_config_error	9.000s	144.544us	50	50	100.00
		aes_stress	18.000s	63.096us	50	50	100.00
V2	key_length	aes_smoke	9.000s	143.070us	50	50	100.00
		aes_config_error	9.000s	144.544us	50	50	100.00
		aes_stress	18.000s	63.096us	50	50	100.00
V2	back2back	aes_stress	18.000s	63.096us	50	50	100.00
		aes_b2b	13.000s	578.037us	50	50	100.00
V2	backpressure	aes_stress	18.000s	63.096us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	143.070us	50	50	100.00
		aes_config_error	9.000s	144.544us	50	50	100.00
		aes_stress	18.000s	63.096us	50	50	100.00
		aes_alert_reset	10.000s	153.369us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	63.693us	50	50	100.00
		aes_config_error	9.000s	144.544us	50	50	100.00
		aes_alert_reset	10.000s	153.369us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	146.602us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	107.556us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	153.369us	50	50	100.00
V2	stress	aes_stress	18.000s	63.096us	50	50	100.00
V2	sideload	aes_stress	18.000s	63.096us	50	50	100.00
		aes_sideload	8.000s	153.409us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	71.479us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	921.829us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	55.003us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	123.035us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	123.035us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	61.692us	5	5	100.00
		aes_csr_rw	3.000s	65.159us	20	20	100.00
		aes_csr_aliasing	6.000s	1.730ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	91.559us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	61.692us	5	5	100.00
		aes_csr_rw	3.000s	65.159us	20	20	100.00
		aes_csr_aliasing	6.000s	1.730ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	91.559us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	75.541us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	339.440us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	960.226us	5	5	100.00
		aes_tl_intg_err	6.000s	1.942ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.942ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	153.369us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	143.070us	50	50	100.00
		aes_stress	18.000s	63.096us	50	50	100.00
		aes_alert_reset	10.000s	153.369us	50	50	100.00
		aes_core_fi	3.283m	10.021ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	95.982us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	62.476us	50	50	100.00
		aes_stress	18.000s	63.096us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	63.096us	50	50	100.00
		aes_sideload	8.000s	153.409us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	62.476us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	62.476us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	62.476us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	62.476us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	62.476us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	63.096us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	63.096us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	247.065us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	247.065us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	16.793ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	247.065us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	153.369us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_ctr_fi	13.000s	62.023us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	247.065us	48	50	96.00
		aes_control_fi	45.000s	10.007ms	284	300	94.67
		aes_cipher_fi	48.000s	16.793ms	329	350	94.00
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.917m	6.349ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.52	94.48	98.71	93.77	97.72	93.33	98.66	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_cipher_fi has 13 failures.
  - 9.aes_cipher_fi.90490097700491255085341467256126344944450624004695503246098502030919394492878
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d47e0135-237e-4a29-870c-75097bc7ec2a
```
  - 85.aes_cipher_fi.67327112890412807499306164726365685384445196489285479439058152270691698432661
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ba7037f0-87b7-4b06-bc0f-65202e151663
```
  - ... and 11 more failures.
- Test aes_control_fi has 7 failures.
  - 62.aes_control_fi.46507034421044842133483861226747077370284663791623057909957200858140296245510
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_control_fi/latest/run.log
```
  Job ID: smart:da775c90-f771-4912-8a15-8d29c03aa8bc
```
  - 130.aes_control_fi.87524694911175812731594620513160583077444551594891372107641213782920309600592
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/130.aes_control_fi/latest/run.log
```
  Job ID: smart:1be35158-f6a9-415f-b644-d16459632df2
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 27.aes_control_fi.12383104205475108663340783093316788176592449024193779503326706984286118945073
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003456832 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003456832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_control_fi.93539121389094936691736260549407930793640983100895424889421411124746671441108
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003236707 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003236707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.45608660781647098023962121919557914778260570823207694436612651627629315275144
Line 769, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9626142180 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9626142180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.68029078457327395320252182016385620150775356989843010977585284624574538903367
Line 1421, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4472421307 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4472421307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 6.aes_cipher_fi.23521604744867038586351800294018182597112558200951700594410240742028971791738
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10034989004 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034989004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.20513903197336211209498617672895817042583644788368170699936217566019753309484
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006076802 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006076802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 5.aes_core_fi.102132962086907359474072890959416855820356977891803362982673140559160480869031
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011194870 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011194870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.21105963025151220352299238683631070525390358478151878094535940774215816100848
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009218179 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009218179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 3 failures:
- Test aes_core_fi has 3 failures.
  - 12.aes_core_fi.89788764281752285895744200635541197781484930466807869487460750306213780475764
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024270741 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x8437a584) == 0x0
  UVM_INFO @ 10024270741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_core_fi.46256570944555772996495981443081723594231170373859830645242859703706323333988
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020573977 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x90137e84) == 0x0
  UVM_INFO @ 10020573977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_csr_mem_rw_with_rand_reset has 2 failures.
  - 13.aes_csr_mem_rw_with_rand_reset.8656414208645884135172634839787120262267735839279202890590791794329563446889
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 733096180 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 733096180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_csr_mem_rw_with_rand_reset.34706966075663864079146529853209481680727652306049059176701006952464590423886
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102847786 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102847786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 41.aes_core_fi.64439176361602901352133903940243888531572380476309318348471018367495744314282
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015050945 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015050945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_core_fi.100141378650565298903371496770886971878379722808511134607175595323565791155292
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009454225 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009454225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

43.aes_fi.34364692052279121945950442951459584341786468753024591266475702818741010549570
Line 5549, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_fi/latest/run.log

  UVM_FATAL @ 274457519 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 274457519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.aes_fi.37192271540747306498628244570239278706640663105848314653457513244452953899213
Line 4958, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log

  UVM_FATAL @  87036991 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  87036991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.46853948504985216997872180628874435465913441226165402950117539419889159362515
    Line 951, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 265289095 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 265289095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.70767542638941734734215507530772616906718785657030098426604810495425257254910
    Line 364, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 232054361 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 232054361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```