AES/UNMASKED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	52.667us	1	1	100.00
V1	smoke	aes_smoke	13.000s	71.630us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	108.600us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	62.875us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.835ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	477.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	68.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	62.875us	20	20	100.00
		aes_csr_aliasing	4.000s	477.583us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	71.630us	50	50	100.00
		aes_config_error	9.000s	120.665us	50	50	100.00
		aes_stress	13.000s	174.982us	50	50	100.00
V2	key_length	aes_smoke	13.000s	71.630us	50	50	100.00
		aes_config_error	9.000s	120.665us	50	50	100.00
		aes_stress	13.000s	174.982us	50	50	100.00
V2	back2back	aes_stress	13.000s	174.982us	50	50	100.00
		aes_b2b	16.000s	107.602us	50	50	100.00
V2	backpressure	aes_stress	13.000s	174.982us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	71.630us	50	50	100.00
		aes_config_error	9.000s	120.665us	50	50	100.00
		aes_stress	13.000s	174.982us	50	50	100.00
		aes_alert_reset	13.000s	173.317us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	82.872us	50	50	100.00
		aes_config_error	9.000s	120.665us	50	50	100.00
		aes_alert_reset	13.000s	173.317us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	103.302us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	314.301us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	173.317us	50	50	100.00
V2	stress	aes_stress	13.000s	174.982us	50	50	100.00
V2	sideload	aes_stress	13.000s	174.982us	50	50	100.00
		aes_sideload	14.000s	77.533us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	93.680us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	1.434ms	10	10	100.00
V2	alert_test	aes_alert_test	15.000s	94.657us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	101.134us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	101.134us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	108.600us	5	5	100.00
		aes_csr_rw	3.000s	62.875us	20	20	100.00
		aes_csr_aliasing	4.000s	477.583us	5	5	100.00
		aes_same_csr_outstanding	9.000s	148.210us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	108.600us	5	5	100.00
		aes_csr_rw	3.000s	62.875us	20	20	100.00
		aes_csr_aliasing	4.000s	477.583us	5	5	100.00
		aes_same_csr_outstanding	9.000s	148.210us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	15.000s	70.090us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	140.993us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.504ms	5	5	100.00
		aes_tl_intg_err	8.000s	1.782ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	1.782ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	173.317us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	71.630us	50	50	100.00
		aes_stress	13.000s	174.982us	50	50	100.00
		aes_alert_reset	13.000s	173.317us	50	50	100.00
		aes_core_fi	27.000s	10.009ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	176.247us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	57.730us	50	50	100.00
		aes_stress	13.000s	174.982us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	174.982us	50	50	100.00
		aes_sideload	14.000s	77.533us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	57.730us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	57.730us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	57.730us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	57.730us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	57.730us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	174.982us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	174.982us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	74.318us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	74.318us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.004ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	74.318us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	173.317us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_ctr_fi	14.000s	105.204us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	74.318us	50	50	100.00
		aes_control_fi	45.000s	15.787ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	319	350	91.14
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.150m	86.490ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.54	94.52	98.71	94.06	97.72	93.33	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_control_fi has 14 failures.
  - 3.aes_control_fi.113013683416056233403850959612878626715722876562516531246905328554558298465553
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:f3b72e54-ff2b-4b32-8d46-2f1c2ebbb2a6
```
  - 19.aes_control_fi.47619963348456356019663836601080599593603556550396175297227184342498171325541
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:57b8bee8-fb56-458d-85d4-1984bbd87cf5
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 20 failures.
  - 3.aes_cipher_fi.65357026147445065263100986158594101899167925463318602486464097636214076793798
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bbe652bb-5cf8-4482-b8ca-152d98a2a606
```
  - 5.aes_cipher_fi.114983001511313418387710082420847273485043880780535992889134021264458514025197
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:929b4de2-2973-4977-8337-69ecf3d26010
```
  - ... and 18 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 0.aes_cipher_fi.61730288908543770680190401543398211979047291058179605803266497544887208412473
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002642000 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002642000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_cipher_fi.29322104186637870089322394050879609506208419240565443535248178232813706658860
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003764907 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003764907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.68325294795189486061731535791135221890788828633717458845475180330197704200664
Line 727, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3399534667 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3399534667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.31158189451625092788903279699860997633048660080160945682137848443760972951870
Line 1510, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3364759398 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3364759398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 196.aes_control_fi.92045496880569932860692448174687680164127404857434341650524576865494107892352
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/196.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007613888 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007613888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 212.aes_control_fi.48246130726172278418736701260044916047230512601649155597689862492294408914930
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/212.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012615082 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012615082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.58090643031389164270690941289541229066972999001877722312425340990651707824638
    Line 731, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 968540746 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 968540746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 3.aes_core_fi.92386405978466047236846283889141431688045956608117452510349504364781889534373
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008502273 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008502273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:68) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 162.aes_control_fi.95578047972626890888536143236003303724422434311818767964348965627305976439275
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/162.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10040598074 ps: (aes_control_fi_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040598074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```