AES/UNMASKED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	126.827us	1	1	100.00
V1	smoke	aes_smoke	9.000s	69.922us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	112.026us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	61.399us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	328.933us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	12.000s	504.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	210.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	61.399us	20	20	100.00
		aes_csr_aliasing	12.000s	504.425us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	69.922us	50	50	100.00
		aes_config_error	9.000s	86.210us	50	50	100.00
		aes_stress	13.000s	71.606us	50	50	100.00
V2	key_length	aes_smoke	9.000s	69.922us	50	50	100.00
		aes_config_error	9.000s	86.210us	50	50	100.00
		aes_stress	13.000s	71.606us	50	50	100.00
V2	back2back	aes_stress	13.000s	71.606us	50	50	100.00
		aes_b2b	24.000s	81.062us	50	50	100.00
V2	backpressure	aes_stress	13.000s	71.606us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	69.922us	50	50	100.00
		aes_config_error	9.000s	86.210us	50	50	100.00
		aes_stress	13.000s	71.606us	50	50	100.00
		aes_alert_reset	14.000s	71.489us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	78.897us	50	50	100.00
		aes_config_error	9.000s	86.210us	50	50	100.00
		aes_alert_reset	14.000s	71.489us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	168.115us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	262.777us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	71.489us	50	50	100.00
V2	stress	aes_stress	13.000s	71.606us	50	50	100.00
V2	sideload	aes_stress	13.000s	71.606us	50	50	100.00
		aes_sideload	8.000s	158.029us	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	121.438us	50	50	100.00
V2	stress_all	aes_stress_all	1.183m	5.668ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	78.247us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	99.690us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	99.690us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	112.026us	5	5	100.00
		aes_csr_rw	8.000s	61.399us	20	20	100.00
		aes_csr_aliasing	12.000s	504.425us	5	5	100.00
		aes_same_csr_outstanding	13.000s	198.255us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	112.026us	5	5	100.00
		aes_csr_rw	8.000s	61.399us	20	20	100.00
		aes_csr_aliasing	12.000s	504.425us	5	5	100.00
		aes_same_csr_outstanding	13.000s	198.255us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	29.000s	102.135us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	92.447us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	967.022us	5	5	100.00
		aes_tl_intg_err	9.000s	303.698us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	303.698us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	71.489us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	69.922us	50	50	100.00
		aes_stress	13.000s	71.606us	50	50	100.00
		aes_alert_reset	14.000s	71.489us	50	50	100.00
		aes_core_fi	3.450m	10.015ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	111.863us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	114.564us	50	50	100.00
		aes_stress	13.000s	71.606us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	71.606us	50	50	100.00
		aes_sideload	8.000s	158.029us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	114.564us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	114.564us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	114.564us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	114.564us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	114.564us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	71.606us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	71.606us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	106.153us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	106.153us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.007ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	106.153us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	71.489us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_ctr_fi	13.000s	65.872us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	106.153us	49	50	98.00
		aes_control_fi	52.000s	10.003ms	276	300	92.00
		aes_cipher_fi	48.000s	10.007ms	328	350	93.71
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	28.000s	646.607us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.50	94.35	98.81	93.71	97.72	93.33	98.85	95.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_cipher_fi has 12 failures.
  - 8.aes_cipher_fi.95323289842949520938451759795099252845871047115032808297892771816723844394088
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2be11bfd-e4a7-4c64-8692-a7b7a032276a
```
  - 22.aes_cipher_fi.112050065255062143359567856958010916444450970921721933865116802696853905581988
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fc49be96-0338-4bbc-953d-c37abed72074
```
  - ... and 10 more failures.
- Test aes_control_fi has 11 failures.
  - 42.aes_control_fi.99461588553639965339280427945560759116200306894352038205486594309563448438719
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job ID: smart:ed320313-8fe5-4ff4-af6c-829e217b613b
```
  - 51.aes_control_fi.17017524626019292470633053156365016050543949529997561990734184222849631393058
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:0ca5bc20-28e6-4d07-8d7e-2aec63a92b7b
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 23.aes_control_fi.114169982507115932533262173575524500866550620906197245074909400223258471699239
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10034310590 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034310590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_control_fi.23642946824391924370199391702732917743755553552822968471170376149275625430074
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011418170 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011418170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 46.aes_cipher_fi.87088146899324025677699684199150271638250638021343790229069535871742910717489
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005481239 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005481239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.70572310963399825647963908339730249917160199017287816760308747802809335726586
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005931895 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005931895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.115315880679059666847568706323620622454275692673376860201748668399689555127691
Line 687, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 482509356 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 482509356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.19761919954945087086161700659160982353401874096728632205874731830495180381048
Line 1292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 594863723 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 594863723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.84438266564254653084017916456432800138462776217695210218501300031503967731665
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020724126 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020724126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_core_fi.1575048415593768601324195298816218371708527115735392534498584121049534145178
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009403660 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009403660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 1.aes_core_fi.16122280455450212656732970690007348812674300287284156984725119305751850403939
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008183279 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008183279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_core_fi.77628402838406602061202115150107772004030193198035936798439760203523412807015
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007650510 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007650510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.63720856183696145327366441348927658876340366154853881023769589913990142754111
Line 1402, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3202564037 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3202564037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.47836974523290951014905309950454672899798170861914837105243348859750721032836
Line 1630, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 988846544 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 988846544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.80823422309659192999506585118531929977871518203651812378164672356670611692156
    Line 576, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 712330317 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 712330317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 24.aes_core_fi.27214908439127964727467553876802782186059740365686399294671946068559268345995
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015150282 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xa0f1a984, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10015150282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 41.aes_fi.108384580457465736141949251444918833209203370254291375864444048409016102410526
    Line 2619, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 27878586 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 27838586 PS)
  UVM_ERROR @  27878586 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  27878586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```