AES/UNMASKED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.107us	1	1	100.00
V1	smoke	aes_smoke	9.000s	104.540us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	85.218us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	54.753us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	3.636ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	396.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	64.633us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	54.753us	20	20	100.00
		aes_csr_aliasing	5.000s	396.202us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	104.540us	50	50	100.00
		aes_config_error	8.000s	78.555us	50	50	100.00
		aes_stress	9.000s	91.040us	50	50	100.00
V2	key_length	aes_smoke	9.000s	104.540us	50	50	100.00
		aes_config_error	8.000s	78.555us	50	50	100.00
		aes_stress	9.000s	91.040us	50	50	100.00
V2	back2back	aes_stress	9.000s	91.040us	50	50	100.00
		aes_b2b	13.000s	662.512us	50	50	100.00
V2	backpressure	aes_stress	9.000s	91.040us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	104.540us	50	50	100.00
		aes_config_error	8.000s	78.555us	50	50	100.00
		aes_stress	9.000s	91.040us	50	50	100.00
		aes_alert_reset	9.000s	166.451us	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	133.697us	50	50	100.00
		aes_config_error	8.000s	78.555us	50	50	100.00
		aes_alert_reset	9.000s	166.451us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	465.960us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	241.214us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	166.451us	50	50	100.00
V2	stress	aes_stress	9.000s	91.040us	50	50	100.00
V2	sideload	aes_stress	9.000s	91.040us	50	50	100.00
		aes_sideload	10.000s	85.838us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	99.457us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	6.721ms	10	10	100.00
V2	alert_test	aes_alert_test	17.000s	57.301us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	89.429us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	89.429us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	85.218us	5	5	100.00
		aes_csr_rw	3.000s	54.753us	20	20	100.00
		aes_csr_aliasing	5.000s	396.202us	5	5	100.00
		aes_same_csr_outstanding	4.000s	130.798us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	85.218us	5	5	100.00
		aes_csr_rw	3.000s	54.753us	20	20	100.00
		aes_csr_aliasing	5.000s	396.202us	5	5	100.00
		aes_same_csr_outstanding	4.000s	130.798us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	74.017us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	100.177us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.432ms	5	5	100.00
		aes_tl_intg_err	6.000s	542.577us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	542.577us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	166.451us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	104.540us	50	50	100.00
		aes_stress	9.000s	91.040us	50	50	100.00
		aes_alert_reset	9.000s	166.451us	50	50	100.00
		aes_core_fi	1.850m	10.040ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	61.662us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	85.001us	50	50	100.00
		aes_stress	9.000s	91.040us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	91.040us	50	50	100.00
		aes_sideload	10.000s	85.838us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	85.001us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	85.001us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	85.001us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	85.001us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	85.001us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	91.040us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	91.040us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	221.825us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	221.825us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	32.836ms	317	350	90.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	221.825us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	166.451us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_ctr_fi	13.000s	53.099us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	221.825us	49	50	98.00
		aes_control_fi	48.000s	10.004ms	268	300	89.33
		aes_cipher_fi	49.000s	32.836ms	317	350	90.57
V2S		TOTAL			914	985	92.79
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.050m	8.511ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1521	1602	94.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.52	94.39	98.75	93.65	97.72	91.11	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
- Test aes_control_fi has 20 failures.
  - 9.aes_control_fi.42842226791828366353910176896308732994430740315138206311589982799874712341470
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:b30ea8d8-e46c-4bc7-a1c1-11d23480243c
```
  - 27.aes_control_fi.97172933732544739356491253899181938853018151632958081157210966494757207132466
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:89814fc8-2e9d-43a8-ab8b-3215e7ddda00
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 17 failures.
  - 56.aes_cipher_fi.74364768940303825671314981009411007998397983930756918344062397789809317924020
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  Job ID: smart:09878743-dc4b-48ad-a52f-e941fc2ac77f
```
  - 58.aes_cipher_fi.24686391977307183490727695978547764170742026703110276778115325229011993860167
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1bd65802-c5e5-49fc-8585-183fb3177cbf
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 0.aes_cipher_fi.16072556577211414263107952657819790107296585481631015503723918649131830098626
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005330369 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005330369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_cipher_fi.2818006711676534735811702232443270360192699062273266352290492625314373169811
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010198360 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010198360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 2.aes_control_fi.41871356261131592502010904146605355727388402124418904726396688510667830644089
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021103467 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021103467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_control_fi.3537426150368482229672201345995959737559367186693422888091249147289553540852
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003510182 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003510182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.46883344805759145075928382178839515340673802963983777541525690948319135826321
Line 684, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8510693251 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8510693251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.105585034838723649035977511906536899678847109101249685060033080401422673935795
Line 1263, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3584267924 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3584267924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.114949121307694796581646943830532305004147651063860233756344629339491614935978
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10033519736 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x80dfc184, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10033519736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_core_fi.24175595723357176684827415730246597318399441643923848846473632096006093987579
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10053205787 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1f4d3984, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10053205787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 28.aes_core_fi.65718677700093143277437851097310815495317583624357895492873522536481440235820
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006888360 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006888360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 31.aes_fi.100193329155483360447868668801714337642221642857066229660855559778618343978860
    Line 6724, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_fi/latest/run.log
```
  UVM_FATAL @  93784007 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  93784007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 37.aes_core_fi.88863502508093420213408780627441888326562036179462106214743425145769364190704
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010884139 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010884139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.68030411265991801380490835715713913136048799135358261568517720556347475955750
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10040261801 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x19567684, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10040261801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 283.aes_control_fi.45149042657086736881221839087787969330886773235798850728466349293671356415913
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/283.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```