AES/UNMASKED Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	84.363us	1	1	100.00
V1	smoke	aes_smoke	4.000s	61.150us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	53.001us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	58.580us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	774.223us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	1.896ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	409.979us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	58.580us	20	20	100.00
		aes_csr_aliasing	7.000s	1.896ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	61.150us	50	50	100.00
		aes_config_error	4.000s	105.072us	50	50	100.00
		aes_stress	5.000s	396.504us	50	50	100.00
V2	key_length	aes_smoke	4.000s	61.150us	50	50	100.00
		aes_config_error	4.000s	105.072us	50	50	100.00
		aes_stress	5.000s	396.504us	50	50	100.00
V2	back2back	aes_stress	5.000s	396.504us	50	50	100.00
		aes_b2b	12.000s	231.389us	50	50	100.00
V2	backpressure	aes_stress	5.000s	396.504us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	61.150us	50	50	100.00
		aes_config_error	4.000s	105.072us	50	50	100.00
		aes_stress	5.000s	396.504us	50	50	100.00
		aes_alert_reset	5.000s	129.638us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	74.972us	50	50	100.00
		aes_config_error	4.000s	105.072us	50	50	100.00
		aes_alert_reset	5.000s	129.638us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	257.305us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	495.787us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	129.638us	50	50	100.00
V2	stress	aes_stress	5.000s	396.504us	50	50	100.00
V2	sideload	aes_stress	5.000s	396.504us	50	50	100.00
		aes_sideload	19.000s	776.602us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	444.148us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	1.417ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	101.216us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	461.109us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	461.109us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	53.001us	5	5	100.00
		aes_csr_rw	3.000s	58.580us	20	20	100.00
		aes_csr_aliasing	7.000s	1.896ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	612.287us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	53.001us	5	5	100.00
		aes_csr_rw	3.000s	58.580us	20	20	100.00
		aes_csr_aliasing	7.000s	1.896ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	612.287us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	6.000s	423.237us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	157.145us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	3.065ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.611ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.611ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	129.638us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	61.150us	50	50	100.00
		aes_stress	5.000s	396.504us	50	50	100.00
		aes_alert_reset	5.000s	129.638us	50	50	100.00
		aes_core_fi	6.767m	10.010ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	55.096us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	62.598us	50	50	100.00
		aes_stress	5.000s	396.504us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	396.504us	50	50	100.00
		aes_sideload	19.000s	776.602us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	62.598us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	62.598us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	62.598us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	62.598us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	62.598us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	396.504us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	396.504us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	188.451us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	188.451us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.004ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	188.451us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	129.638us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_ctr_fi	4.000s	58.391us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	188.451us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	48.000s	10.004ms	326	350	93.14
V2S		TOTAL			942	985	95.63
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	4.159ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1549	1602	96.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.43	94.18	98.81	93.57	97.72	93.33	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 8 failures.
  - 9.aes_control_fi.23910275872531386870145068025987881311177997757532929315570331729391642845420
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:12e408d3-05f0-444d-931d-1f71306d528f
```
  - 18.aes_control_fi.70399258597616373218657772613083734800304563395107536585108158552222938979566
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:70173dfe-8619-4f96-bfdc-79aa9cf5a1bc
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 17 failures.
  - 24.aes_cipher_fi.76764132524216113659120958748140645587259407301687491953937479741959055416828
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job ID: smart:28106fd5-143c-4d13-a93a-2a99c058ce90
```
  - 50.aes_cipher_fi.81357325598521428908469797216734001904588906996902088255925729747319034462609
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8e0cf11c-18e3-4b5c-9ce0-080a3958b279
```
  - ... and 15 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 14.aes_control_fi.66846504800999167369988027808890934628715626425888139591904772737307959262152
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005755995 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005755995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_control_fi.105265378596675266537317012893337878179194708137701019395235686862007127139681
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003480068 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003480068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 1.aes_cipher_fi.96726394631902946458462835837887292874032592605880721161963781719152375917112
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009704847 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009704847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 87.aes_cipher_fi.43831067515656962376819370778532216633191178720797369551293195006635384511656
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/87.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003773406 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003773406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.4413660487881426346645129446823217103520325936979996309365079211878846762170
Line 509, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1639843820 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1639843820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.30302578390370881878261889723675379952160349939828769213199614927709620859489
Line 1733, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1032102089 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1032102089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.46644057074683305474600302844035009666020465579434282742417359331301680656372
Line 1708, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2458360158 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2458360158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.7070213227951370450149013265958142966473794510460866272495730588206345113321
Line 495, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 884568329 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 884568329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

9.aes_stress_all_with_rand_reset.23614813414776311982055029242201886399264060346949585373414695809246678299925
Line 465, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 51584057 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 51574057 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 51584057 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 51574057 PS)
  UVM_ERROR @  51584057 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.29379699206217505632264497572103003395235832257805652517722407191249173226658
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010196279 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5e13b084, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10010196279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```