AES/UNMASKED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	60.097us	1	1	100.00
V1	smoke	aes_smoke	6.000s	252.195us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	104.732us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	77.508us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	5.720ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	94.534us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	150.624us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	77.508us	20	20	100.00
		aes_csr_aliasing	5.000s	94.534us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	252.195us	50	50	100.00
		aes_config_error	9.000s	116.263us	50	50	100.00
		aes_stress	9.000s	53.359us	50	50	100.00
V2	key_length	aes_smoke	6.000s	252.195us	50	50	100.00
		aes_config_error	9.000s	116.263us	50	50	100.00
		aes_stress	9.000s	53.359us	50	50	100.00
V2	back2back	aes_stress	9.000s	53.359us	50	50	100.00
		aes_b2b	13.000s	134.513us	50	50	100.00
V2	backpressure	aes_stress	9.000s	53.359us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	252.195us	50	50	100.00
		aes_config_error	9.000s	116.263us	50	50	100.00
		aes_stress	9.000s	53.359us	50	50	100.00
		aes_alert_reset	6.000s	128.120us	49	50	98.00
V2	failure_test	aes_man_cfg_err	13.000s	90.821us	50	50	100.00
		aes_config_error	9.000s	116.263us	50	50	100.00
		aes_alert_reset	6.000s	128.120us	49	50	98.00
V2	trigger_clear_test	aes_clear	15.000s	197.636us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	111.959us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	128.120us	49	50	98.00
V2	stress	aes_stress	9.000s	53.359us	50	50	100.00
V2	sideload	aes_stress	9.000s	53.359us	50	50	100.00
		aes_sideload	9.000s	66.633us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	66.745us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	2.253ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	54.028us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	277.085us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	277.085us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	104.732us	5	5	100.00
		aes_csr_rw	4.000s	77.508us	20	20	100.00
		aes_csr_aliasing	5.000s	94.534us	5	5	100.00
		aes_same_csr_outstanding	5.000s	89.497us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	104.732us	5	5	100.00
		aes_csr_rw	4.000s	77.508us	20	20	100.00
		aes_csr_aliasing	5.000s	94.534us	5	5	100.00
		aes_same_csr_outstanding	5.000s	89.497us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	9.000s	71.440us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	163.352us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	24.000s	9.766ms	5	5	100.00
		aes_tl_intg_err	5.000s	324.122us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	324.122us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	128.120us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	252.195us	50	50	100.00
		aes_stress	9.000s	53.359us	50	50	100.00
		aes_alert_reset	6.000s	128.120us	49	50	98.00
		aes_core_fi	3.383m	10.016ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	73.646us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	66.698us	50	50	100.00
		aes_stress	9.000s	53.359us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	53.359us	50	50	100.00
		aes_sideload	9.000s	66.633us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	66.698us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	66.698us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	66.698us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	66.698us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	66.698us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	53.359us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	53.359us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	185.653us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	185.653us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.003ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	185.653us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	128.120us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_ctr_fi	5.000s	50.780us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	185.653us	49	50	98.00
		aes_control_fi	43.000s	10.073ms	270	300	90.00
		aes_cipher_fi	50.000s	10.003ms	321	350	91.71
V2S		TOTAL			922	985	93.60
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.500m	13.432ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1528	1602	95.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.46	94.26	98.77	93.80	97.64	91.11	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_cipher_fi has 15 failures.
  - 3.aes_cipher_fi.82201085628068739902674221409882979924703190765346061179753795829429087864028
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fcdb7e7a-6966-4a08-8caa-c6d75187eed0
```
  - 19.aes_cipher_fi.109626718787630609725623166087828419727213592248605999164341664945971894099037
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bffcb187-1418-4a95-8b5a-358513412ad1
```
  - ... and 13 more failures.
- Test aes_control_fi has 17 failures.
  - 39.aes_control_fi.23550411517950572109823420480254873061726002985055818870433539704400522060146
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:058c6711-1b29-49f2-a24f-0a22ee2e598a
```
  - 54.aes_control_fi.28605092574083649400627881423625809652392900367340697986846355025278093415795
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  Job ID: smart:bdfe9edd-8438-4ee8-a546-d0ca9e355ba1
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 65.aes_cipher_fi.97163694853775899499228606572107254918403453675456308105231787299042885460990
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003827099 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003827099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_cipher_fi.104471569344396232815646085105302417777596538229710296403355964716506041315041
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008040510 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008040510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 6.aes_control_fi.62087973906328762641244936753192796991638708109604105915512228436717125045964
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005035091 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005035091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_control_fi.77046733041869679219102090535507915117254500420061873866739021342042755005124
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018551213 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018551213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

1.aes_stress_all_with_rand_reset.113951223222614583772959424189371743312463406765099896187494873525654179201431
Line 667, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 450107180 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 450107180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.43639474029334120678484260712455318718293746007256490787814230195266548930080
Line 1201, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5912650002 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5912650002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 1.aes_core_fi.89616248518957168504218531133422974846750167931285781174635368349125842083182
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002655004 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002655004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_core_fi.40837993767897198967406954721657718443973705051565782555468028389843797870509
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016533060 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016533060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.67736134786099728890284044619466553274984560019269159780090324611707953252463
    Line 943, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 985433276 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 985433276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.11140997727265930969744304207862116049978550514151187139403439151767065603346
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015506997 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x72cbd284, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10015506997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 28.aes_fi.104172065099391667791842548383152086712268800596260448699798493513350864215490
    Line 7578, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_fi/latest/run.log
```
  UVM_FATAL @  19259861 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  19259861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

36.aes_alert_reset.50068796764159897484507601106101456579436536383424898112722700022588158802863
Line 2285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 8807984 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8797567 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 8807984 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8797567 PS)
  UVM_ERROR @   8807984 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut