AES/UNMASKED Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	77.808us	1	1	100.00
V1	smoke	aes_smoke	18.000s	184.371us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	106.743us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	52.069us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1.150ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	304.706us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	515.816us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	52.069us	20	20	100.00
		aes_csr_aliasing	4.000s	304.706us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	184.371us	50	50	100.00
		aes_config_error	13.000s	131.306us	50	50	100.00
		aes_stress	15.000s	131.022us	50	50	100.00
V2	key_length	aes_smoke	18.000s	184.371us	50	50	100.00
		aes_config_error	13.000s	131.306us	50	50	100.00
		aes_stress	15.000s	131.022us	50	50	100.00
V2	back2back	aes_stress	15.000s	131.022us	50	50	100.00
		aes_b2b	14.000s	357.299us	50	50	100.00
V2	backpressure	aes_stress	15.000s	131.022us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	184.371us	50	50	100.00
		aes_config_error	13.000s	131.306us	50	50	100.00
		aes_stress	15.000s	131.022us	50	50	100.00
		aes_alert_reset	10.000s	70.069us	49	50	98.00
V2	failure_test	aes_man_cfg_err	9.000s	76.499us	50	50	100.00
		aes_config_error	13.000s	131.306us	50	50	100.00
		aes_alert_reset	10.000s	70.069us	49	50	98.00
V2	trigger_clear_test	aes_clear	10.000s	139.031us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	2.296ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	70.069us	49	50	98.00
V2	stress	aes_stress	15.000s	131.022us	50	50	100.00
V2	sideload	aes_stress	15.000s	131.022us	50	50	100.00
		aes_sideload	9.000s	152.511us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	85.644us	50	50	100.00
V2	stress_all	aes_stress_all	19.000s	388.075us	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	76.728us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	82.994us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	82.994us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	106.743us	5	5	100.00
		aes_csr_rw	3.000s	52.069us	20	20	100.00
		aes_csr_aliasing	4.000s	304.706us	5	5	100.00
		aes_same_csr_outstanding	4.000s	117.946us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	106.743us	5	5	100.00
		aes_csr_rw	3.000s	52.069us	20	20	100.00
		aes_csr_aliasing	4.000s	304.706us	5	5	100.00
		aes_same_csr_outstanding	4.000s	117.946us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	26.000s	1.104ms	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	84.378us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	758.642us	5	5	100.00
		aes_tl_intg_err	6.000s	123.508us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	123.508us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	70.069us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	184.371us	50	50	100.00
		aes_stress	15.000s	131.022us	50	50	100.00
		aes_alert_reset	10.000s	70.069us	49	50	98.00
		aes_core_fi	1.000m	10.048ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	132.546us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	73.005us	50	50	100.00
		aes_stress	15.000s	131.022us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	131.022us	50	50	100.00
		aes_sideload	9.000s	152.511us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	73.005us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	73.005us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	73.005us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	73.005us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	73.005us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	131.022us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	131.022us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	71.932us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	71.932us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	65.640ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	71.932us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	70.069us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_ctr_fi	14.000s	104.014us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	71.932us	48	50	96.00
		aes_control_fi	51.000s	18.782ms	275	300	91.67
		aes_cipher_fi	51.000s	65.640ms	324	350	92.57
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	10.467m	28.433ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.50	94.35	98.81	93.65	97.72	93.33	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 14 failures.
  - 19.aes_cipher_fi.113699542411249660334593715087272832678073175684200163486413521051318390720611
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c75c96df-f9e3-4b58-aa5c-181a571b72c5
```
  - 52.aes_cipher_fi.25294764268783882375406553085703320312989018664092218988848159986859184029697
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5e9f1375-1a4c-4fa7-b9b6-84df433de829
```
  - ... and 12 more failures.
- Test aes_control_fi has 15 failures.
  - 29.aes_control_fi.101758319258970759782433113031755755841622560752284130991025555660154711940320
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:186a1272-c6c4-4205-8176-5ceaa134cf05
```
  - 36.aes_control_fi.19595180716742209098318551564797235532454756515290926508806504267779861654797
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:53eccb2e-09f4-4ef9-81ce-116852487f58
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 16.aes_cipher_fi.82528162650605643581467866894965385955942273188608142761714851812012010989815
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004294383 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004294383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 76.aes_cipher_fi.79385862054436934170073813329342703650782694549656826451808181408856253968964
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004742497 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004742497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 67.aes_control_fi.67289800462989283094648556404897045978950834498174086985534784856878489334861
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007662183 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007662183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_control_fi.51867860386606912210162545951474241454008770628501728650956532576019175052581
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002783951 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002783951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.54800422191939808659694697220855658355244621223536713916638856893362716535868
Line 826, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15909966440 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15909966440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.113216267042406472655522243580705853282894583595680919593890841708476012676797
Line 477, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 802807387 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 802807387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

3.aes_stress_all_with_rand_reset.18081132328754782945246893736330025947640087975459523110473858352889011438268
Line 1217, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 3941631713 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 3941591713 PS)
  UVM_ERROR @ 3941631713 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 3941631713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

16.aes_fi.45633320511265752437828021577597722006722029778041220603610057453824512400301
Line 657, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 6285921 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 6275921 PS)
  UVM_ERROR @   6285921 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   6285921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

6.aes_stress_all_with_rand_reset.54123545240883938003896466601267151794071506364518563061760473193014036647327
Line 590, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 681779304 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 681779304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_stress_all_with_rand_reset.101494313243733506944731923338551138948241676797206254681061872594252847649180
Line 1299, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 533057549 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 533057549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 1 failures.

30.aes_alert_reset.78333656088435016053847752638534448345502150565456954056382781695104288228146
Line 1669, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 10248976 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10230794 PS)
  UVM_ERROR @  10248976 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  10248976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

46.aes_fi.32037587465371631748292268552972011708976254067901765883868703054640334128946
Line 3714, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 46862037 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 46822037 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 46862037 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 46822037 PS)
  UVM_ERROR @  46862037 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.106838212492476802518214368556220229585818801394532824755246067118837009126975
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10138558149 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1b335384, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10138558149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 69.aes_core_fi.115081913542440022447686480612826883955881409048572333392944570501659414292929
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10048257861 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1929ac84, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10048257861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```