AES/UNMASKED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	119.178us	1	1	100.00
V1	smoke	aes_smoke	13.000s	85.921us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	64.743us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	54.275us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	4.160ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	125.643us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	89.152us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	54.275us	20	20	100.00
		aes_csr_aliasing	6.000s	125.643us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	85.921us	50	50	100.00
		aes_config_error	10.000s	102.845us	50	50	100.00
		aes_stress	15.000s	143.929us	50	50	100.00
V2	key_length	aes_smoke	13.000s	85.921us	50	50	100.00
		aes_config_error	10.000s	102.845us	50	50	100.00
		aes_stress	15.000s	143.929us	50	50	100.00
V2	back2back	aes_stress	15.000s	143.929us	50	50	100.00
		aes_b2b	16.000s	226.673us	50	50	100.00
V2	backpressure	aes_stress	15.000s	143.929us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	85.921us	50	50	100.00
		aes_config_error	10.000s	102.845us	50	50	100.00
		aes_stress	15.000s	143.929us	50	50	100.00
		aes_alert_reset	9.000s	283.982us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	80.504us	50	50	100.00
		aes_config_error	10.000s	102.845us	50	50	100.00
		aes_alert_reset	9.000s	283.982us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	204.441us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	4.987ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	283.982us	50	50	100.00
V2	stress	aes_stress	15.000s	143.929us	50	50	100.00
V2	sideload	aes_stress	15.000s	143.929us	50	50	100.00
		aes_sideload	13.000s	81.080us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	91.489us	50	50	100.00
V2	stress_all	aes_stress_all	44.000s	5.989ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	88.354us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	139.705us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	139.705us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	64.743us	5	5	100.00
		aes_csr_rw	4.000s	54.275us	20	20	100.00
		aes_csr_aliasing	6.000s	125.643us	5	5	100.00
		aes_same_csr_outstanding	4.000s	320.523us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	64.743us	5	5	100.00
		aes_csr_rw	4.000s	54.275us	20	20	100.00
		aes_csr_aliasing	6.000s	125.643us	5	5	100.00
		aes_same_csr_outstanding	4.000s	320.523us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	202.562us	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	113.195us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	2.198ms	5	5	100.00
		aes_tl_intg_err	5.000s	223.282us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	223.282us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	283.982us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	85.921us	50	50	100.00
		aes_stress	15.000s	143.929us	50	50	100.00
		aes_alert_reset	9.000s	283.982us	50	50	100.00
		aes_core_fi	39.000s	10.002ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	55.761us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	68.398us	50	50	100.00
		aes_stress	15.000s	143.929us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	143.929us	50	50	100.00
		aes_sideload	13.000s	81.080us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	68.398us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	68.398us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	68.398us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	68.398us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	68.398us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	143.929us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	143.929us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	118.017us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	118.017us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	31.528ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	118.017us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	283.982us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_ctr_fi	7.000s	54.102us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	118.017us	49	50	98.00
		aes_control_fi	46.000s	10.012ms	283	300	94.33
		aes_cipher_fi	48.000s	31.528ms	324	350	92.57
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.667m	24.889ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.44	94.22	98.73	93.74	97.64	93.33	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_cipher_fi has 14 failures.
  - 23.aes_cipher_fi.93128674638500980143638146584232384222281392146315285595851032630434464156376
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a31010bf-93f9-45ff-a2cc-79754f059b68
```
  - 77.aes_cipher_fi.62806519130182220680785185475055890274001238061679187587508305330480591562
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/77.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fb598a77-8bac-4316-ba3a-34dacf3e8883
```
  - ... and 12 more failures.
- Test aes_control_fi has 14 failures.
  - 33.aes_control_fi.53533676630096729923458667730316062379518278299727399152738193665947109453981
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job ID: smart:44322d74-3f33-4d2e-8cc1-4359aa4eaee4
```
  - 79.aes_control_fi.85283698306445254472962631833934660211055287278969219627433980696385317536151
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/79.aes_control_fi/latest/run.log
```
  Job ID: smart:65b6eb25-3378-49c6-98da-9e813243e42d
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 32.aes_cipher_fi.107663222972047763777066811587527078872667293958956643679039066723131359203861
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003058794 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003058794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_cipher_fi.46660324637682627198276121513310916839077154815253993802914412554189499685048
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009068976 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009068976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.57324258366814258489962528098120335628321145913337067515181459496447408608561
Line 822, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1738011052 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1738011052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.73954826653379973975058138730259589737137094556575221485849138878044364573478
Line 1508, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10426386879 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10426386879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.79554783043713215639530589389373706310534759052266038038863076161879502564958
Line 1272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 716410641 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 716410641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.34267135868585125221428609684888088679172429803621045326745293264266792992097
Line 1149, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2918094419 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2918094419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 104.aes_control_fi.3488812494362175430572862226199936267676393298127992289292419338640985337742
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/104.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011702281 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011702281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 176.aes_control_fi.111860299345539288232304370981535132401876479648041144533202265723880360529386
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/176.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008738514 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008738514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.43798415619134279808718639879837925617598301261231860743085326389734946084418
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005799004 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005799004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_core_fi.64681902030625824723061278112529488146426396921439768124332603211435764744227
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002150499 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002150499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:552) [aes_fi_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_fi has 1 failures.
  - 20.aes_fi.50597528396967206269055530925994104907064966860352229172734871803987170835554
    Line 3922, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log
```
  UVM_ERROR @  26744128 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  26744128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 63.aes_cipher_fi.37322226983222898542728488593028966186189568510126318168304545008168723025451
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  16291099 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  16291099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```