AES/UNMASKED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	62.326us	1	1	100.00
V1	smoke	aes_smoke	14.000s	91.120us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	116.930us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	102.115us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.023ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	1.047ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	93.373us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	102.115us	20	20	100.00
		aes_csr_aliasing	4.000s	1.047ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	91.120us	50	50	100.00
		aes_config_error	19.000s	194.297us	50	50	100.00
		aes_stress	9.000s	70.369us	50	50	100.00
V2	key_length	aes_smoke	14.000s	91.120us	50	50	100.00
		aes_config_error	19.000s	194.297us	50	50	100.00
		aes_stress	9.000s	70.369us	50	50	100.00
V2	back2back	aes_stress	9.000s	70.369us	50	50	100.00
		aes_b2b	12.000s	164.933us	50	50	100.00
V2	backpressure	aes_stress	9.000s	70.369us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	91.120us	50	50	100.00
		aes_config_error	19.000s	194.297us	50	50	100.00
		aes_stress	9.000s	70.369us	50	50	100.00
		aes_alert_reset	9.000s	135.813us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	113.351us	50	50	100.00
		aes_config_error	19.000s	194.297us	50	50	100.00
		aes_alert_reset	9.000s	135.813us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	85.527us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	110.251us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	135.813us	50	50	100.00
V2	stress	aes_stress	9.000s	70.369us	50	50	100.00
V2	sideload	aes_stress	9.000s	70.369us	50	50	100.00
		aes_sideload	9.000s	197.737us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	158.837us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	946.430us	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	94.154us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	2.436ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	2.436ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	116.930us	5	5	100.00
		aes_csr_rw	3.000s	102.115us	20	20	100.00
		aes_csr_aliasing	4.000s	1.047ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.501ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	116.930us	5	5	100.00
		aes_csr_rw	3.000s	102.115us	20	20	100.00
		aes_csr_aliasing	4.000s	1.047ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.501ms	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	700.017us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	81.826us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	926.800us	5	5	100.00
		aes_tl_intg_err	5.000s	150.594us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	150.594us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	135.813us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	91.120us	50	50	100.00
		aes_stress	9.000s	70.369us	50	50	100.00
		aes_alert_reset	9.000s	135.813us	50	50	100.00
		aes_core_fi	13.000s	89.123us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	83.620us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	155.628us	50	50	100.00
		aes_stress	9.000s	70.369us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	70.369us	50	50	100.00
		aes_sideload	9.000s	197.737us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	155.628us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	155.628us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	155.628us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	155.628us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	155.628us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	70.369us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	70.369us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	384.272us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	384.272us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	384.272us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	135.813us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_ctr_fi	8.000s	88.081us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	384.272us	48	50	96.00
		aes_control_fi	47.000s	10.003ms	281	300	93.67
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	11.633m	26.172ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.52	94.39	98.77	93.80	97.72	91.11	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_cipher_fi has 16 failures.
  - 5.aes_cipher_fi.26199310730974334300582324458584233542774591421467744778047807206668552341760
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7993e3b2-f311-4fd4-99cc-539d5f038262
```
  - 6.aes_cipher_fi.50707521654610978837880043634359506433603494175845721553863501273151570443664
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a3817fa0-cf75-4773-af57-2a6142abae57
```
  - ... and 14 more failures.
- Test aes_control_fi has 10 failures.
  - 6.aes_control_fi.59918295125851778489536997157507411029687260450028543866757782204263717400448
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:5ab2adac-d7a7-4b5a-9449-88109578da8f
```
  - 35.aes_control_fi.94076457122194231097991765470099838190264094091818296773507541005434422322807
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:cb1d7c2d-105b-4566-85e2-dfb2a3d88568
```
  - ... and 8 more failures.
- Test aes_ctr_fi has 1 failures.
  - 33.aes_ctr_fi.18998458256058032496376941539740373089860407487385282853113409192119689940367
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_ctr_fi/latest/run.log
```
  Job ID: smart:c8f9b26a-0774-48f7-a10a-117199b84c61
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 17.aes_cipher_fi.69838288824663184138526130706490329309779063152553520857494341662895779942093
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036412989 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036412989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.42794096697523809280140090984028034860310138154003479117189528416258793146133
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006180017 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006180017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.91642995393047875443488300485823021780330969511277235400015204929503137035091
Line 586, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5200333006 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5200333006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.84030405095016373164293640068090979845645355062283045867584633188354395857958
Line 632, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1123254821 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1123254821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 16.aes_control_fi.88646285946424879246220907729544397982014586912729805025748969996717997385399
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028478861 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028478861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 93.aes_control_fi.82304309066535429982563977875147846090881574572672251667747513136874246868983
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011985591 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011985591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.63529587709315024537287836819696789292271580425780038114668385509132759556778
    Line 1294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 694987599 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 694987599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 16.aes_fi.43607595456221504601311407085572415522751662232257686723405367205261652970580
    Line 5382, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_fi/latest/run.log
```
  UVM_FATAL @  30302404 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  30302404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 25.aes_fi.41115898952628439466622612320929372610993922057344495785144072127560825928070
    Line 2996, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 17022674 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 16999947 PS)
  UVM_ERROR @  17022674 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  17022674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```