AES/UNMASKED Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	73.793us	1	1	100.00
V1	smoke	aes_smoke	8.000s	56.619us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	115.356us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	123.550us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	3.044ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	285.070us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	89.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	123.550us	20	20	100.00
		aes_csr_aliasing	4.000s	285.070us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	56.619us	50	50	100.00
		aes_config_error	13.000s	72.975us	50	50	100.00
		aes_stress	14.000s	60.546us	50	50	100.00
V2	key_length	aes_smoke	8.000s	56.619us	50	50	100.00
		aes_config_error	13.000s	72.975us	50	50	100.00
		aes_stress	14.000s	60.546us	50	50	100.00
V2	back2back	aes_stress	14.000s	60.546us	50	50	100.00
		aes_b2b	17.000s	123.268us	50	50	100.00
V2	backpressure	aes_stress	14.000s	60.546us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	56.619us	50	50	100.00
		aes_config_error	13.000s	72.975us	50	50	100.00
		aes_stress	14.000s	60.546us	50	50	100.00
		aes_alert_reset	11.000s	69.131us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	52.642us	50	50	100.00
		aes_config_error	13.000s	72.975us	50	50	100.00
		aes_alert_reset	11.000s	69.131us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	197.840us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	721.388us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	69.131us	50	50	100.00
V2	stress	aes_stress	14.000s	60.546us	50	50	100.00
V2	sideload	aes_stress	14.000s	60.546us	50	50	100.00
		aes_sideload	14.000s	115.045us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	227.276us	50	50	100.00
V2	stress_all	aes_stress_all	38.000s	2.809ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	61.737us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	371.310us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	371.310us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	115.356us	5	5	100.00
		aes_csr_rw	8.000s	123.550us	20	20	100.00
		aes_csr_aliasing	4.000s	285.070us	5	5	100.00
		aes_same_csr_outstanding	9.000s	289.423us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	115.356us	5	5	100.00
		aes_csr_rw	8.000s	123.550us	20	20	100.00
		aes_csr_aliasing	4.000s	285.070us	5	5	100.00
		aes_same_csr_outstanding	9.000s	289.423us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	337.895us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	137.763us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	797.773us	5	5	100.00
		aes_tl_intg_err	8.000s	1.258ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	1.258ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	69.131us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	56.619us	50	50	100.00
		aes_stress	14.000s	60.546us	50	50	100.00
		aes_alert_reset	11.000s	69.131us	50	50	100.00
		aes_core_fi	39.000s	10.022ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	91.539us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	58.799us	50	50	100.00
		aes_stress	14.000s	60.546us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	60.546us	50	50	100.00
		aes_sideload	14.000s	115.045us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	58.799us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	58.799us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	58.799us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	58.799us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	58.799us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	60.546us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	60.546us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	243.750us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	243.750us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	24.257ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	243.750us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	69.131us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_ctr_fi	8.000s	67.331us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	243.750us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	277	300	92.33
		aes_cipher_fi	48.000s	24.257ms	318	350	90.86
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	327.503us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	97.52	94.39	98.81	93.83	97.72	93.33	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_cipher_fi has 18 failures.
  - 1.aes_cipher_fi.59022762659494765694300028349372024377588735638689886337217623621238735129669
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ade735f1-b42d-4c67-885a-a8ea5fb7a329
```
  - 15.aes_cipher_fi.109348177235700595882185196061803898908399250009077225997268984096382466100127
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c2dc50e8-a172-4320-8268-8be20e82d6ec
```
  - ... and 16 more failures.
- Test aes_ctr_fi has 1 failures.
  - 21.aes_ctr_fi.43119841515376212613745019689317800234804247471599267142705388795009087722981
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_ctr_fi/latest/run.log
```
  Job ID: smart:a1700d4e-ab67-4e5c-a399-e420757ce9e8
```
- Test aes_control_fi has 14 failures.
  - 36.aes_control_fi.26691604014174987660377033654414488418279048968656412612838513360082386277149
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:12129997-b20c-4cf0-8884-8ed5ae790b1f
```
  - 40.aes_control_fi.109482325198440849099076067527161265816282941601737418842299457203987210479148
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:d53e1154-e732-4ed7-abfc-c9303e9ed044
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 58.aes_cipher_fi.41472619174309883445752083290895107765555382708942202074403229660685033354621
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10070573481 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10070573481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_cipher_fi.23000422309298134318275328732038772623017871452229855512243052119042464523390
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004013802 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004013802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 8.aes_control_fi.46332566321782247416462949795698303134973377440864170689846577208688629144276
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003099043 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003099043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_control_fi.31512455855885359550475596771180100052257948653634054468702141926969014290698
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004545823 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004545823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 11.aes_core_fi.25613887919991537459143619410219505908150721528722865467983823436834812406616
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008603949 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008603949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_core_fi.97557544419509420597520466544172704547810314328479238033005420570446634651961
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035126637 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035126637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.15836110045819323388212114181688029292246546030371587250032138985089455972504
Line 388, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  58268417 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  58268417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.57316220663882338418022536638520709291669415590299737283391034830384025378657
Line 719, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1138707825 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1138707825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.3252095650995296226612229966633109794635363902379434474526730958082135388640
Line 1212, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 327502718 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 327502718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.83596035915429005125554275501014890625805609802678395666451722422373555037763
Line 1257, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 690837386 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 690837386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.103468556810972439869478380776944295976285856770646268216604276391271658631365
    Line 338, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  97809720 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  97809720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.64145502379575494859190775422741046644169990791888599771757114583231324340318
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 827479186 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 827479186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.64969885060097497966167877605310580873974271040247008333161095687995475449583
    Line 860, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1876487629 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1876487629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.76933573453890741096279258686651452014709808374361246793040907579599437453084
    Line 907, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 813046329 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 813046329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 26.aes_cipher_fi.76959190236466905684950107398139602208940090468365194917881120528368769449548
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @   7851999 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   7851999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```