AES/UNMASKED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	56.693us	1	1	100.00
V1	smoke	aes_smoke	8.000s	54.377us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	70.080us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	59.758us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	670.114us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	203.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	155.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	59.758us	20	20	100.00
		aes_csr_aliasing	10.000s	203.718us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	54.377us	50	50	100.00
		aes_config_error	12.000s	71.045us	50	50	100.00
		aes_stress	8.000s	148.341us	50	50	100.00
V2	key_length	aes_smoke	8.000s	54.377us	50	50	100.00
		aes_config_error	12.000s	71.045us	50	50	100.00
		aes_stress	8.000s	148.341us	50	50	100.00
V2	back2back	aes_stress	8.000s	148.341us	50	50	100.00
		aes_b2b	17.000s	162.034us	50	50	100.00
V2	backpressure	aes_stress	8.000s	148.341us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	54.377us	50	50	100.00
		aes_config_error	12.000s	71.045us	50	50	100.00
		aes_stress	8.000s	148.341us	50	50	100.00
		aes_alert_reset	8.000s	113.916us	48	50	96.00
V2	failure_test	aes_man_cfg_err	7.000s	110.788us	50	50	100.00
		aes_config_error	12.000s	71.045us	50	50	100.00
		aes_alert_reset	8.000s	113.916us	48	50	96.00
V2	trigger_clear_test	aes_clear	13.000s	253.730us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	166.085us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	113.916us	48	50	96.00
V2	stress	aes_stress	8.000s	148.341us	50	50	100.00
V2	sideload	aes_stress	8.000s	148.341us	50	50	100.00
		aes_sideload	13.000s	411.610us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	130.050us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	571.035us	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	83.725us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	98.553us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	98.553us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	70.080us	5	5	100.00
		aes_csr_rw	3.000s	59.758us	20	20	100.00
		aes_csr_aliasing	10.000s	203.718us	5	5	100.00
		aes_same_csr_outstanding	8.000s	213.451us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	70.080us	5	5	100.00
		aes_csr_rw	3.000s	59.758us	20	20	100.00
		aes_csr_aliasing	10.000s	203.718us	5	5	100.00
		aes_same_csr_outstanding	8.000s	213.451us	20	20	100.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	8.000s	133.296us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	321.573us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.321ms	5	5	100.00
		aes_tl_intg_err	9.000s	219.840us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	219.840us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	113.916us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	54.377us	50	50	100.00
		aes_stress	8.000s	148.341us	50	50	100.00
		aes_alert_reset	8.000s	113.916us	48	50	96.00
		aes_core_fi	31.000s	10.148ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	77.992us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	58.822us	50	50	100.00
		aes_stress	8.000s	148.341us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	148.341us	50	50	100.00
		aes_sideload	13.000s	411.610us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	58.822us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	58.822us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	58.822us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	58.822us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	58.822us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	148.341us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	148.341us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	513.936us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	513.936us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	31.531ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	513.936us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	113.916us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_ctr_fi	8.000s	77.549us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	513.936us	50	50	100.00
		aes_control_fi	46.000s	54.326ms	273	300	91.00
		aes_cipher_fi	50.000s	31.531ms	329	350	94.00
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.017m	62.375ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.46	94.26	98.77	93.63	97.72	90.37	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 15 failures.
  - 16.aes_control_fi.54098753812932607415938365506665859366803666052502420307364492161428815609223
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:66f3c6f3-53b0-4b26-80b1-a9cdd7ed67a7
```
  - 20.aes_control_fi.111746189772268136700031701835849103847282712628690983568378351444422947049204
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:eeb9c269-c3bb-49f5-ac64-813e6779c88b
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 12 failures.
  - 29.aes_cipher_fi.16232735608254762053366659712352985841922170307791682831184930803101275287383
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job ID: smart:71a27f39-e3aa-4ec8-a4d3-0c8de8b08851
```
  - 57.aes_cipher_fi.14999513563516117506728672841391049620063525817620216026037646641625995581466
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2f735490-7b27-4c27-b323-8554a4139e49
```
  - ... and 10 more failures.
- Test aes_ctr_fi has 1 failures.
  - 31.aes_ctr_fi.29758495356248645304431382846971974114572107377839185426080995653699834860668
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_ctr_fi/latest/run.log
```
  Job ID: smart:16f684ad-24c1-4c7f-8a46-686fbabaa1d2
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 6.aes_control_fi.104169400406144186179350766988209863361370862360203516845630705242790561735140
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013438285 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013438285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_control_fi.99294067373548854119640788579839862230754807915269845822787426733867858094579
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018644546 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018644546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 35.aes_cipher_fi.32556096098050253062092052198795469578823838243909079355298721681437243401611
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008170753 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008170753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_cipher_fi.68349150677433649744438099064229669936264852581048593155735837743324376539834
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005854100 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005854100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.41763440715636631376547072830984831392395293655310930191206752109777355266301
Line 1276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62374554882 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 62374554882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.99209071971796831165029553555561067131769407859654153338102404644413516765880
Line 756, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 730584556 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 730584556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.112054833698357376549293619201441395033497417881563182950205608053526709085508
Line 1175, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3813354530 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3813354530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.111728929439082901701842888787487055182329459863845960084527809634573608446079
Line 1040, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2598297294 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2598297294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 2 failures.

9.aes_alert_reset.94616325846517497701135859025206504853465173203346310106997865411321444554295
Line 617, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 32808974 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 32642307 PS)
  UVM_ERROR @  32808974 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  32808974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aes_alert_reset.113828718659590108050252810954281223462668934350359268381027755442085667453353
Line 4308, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 44910170 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 44870170 PS)
  UVM_ERROR @  44910170 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  44910170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:549) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 8.aes_stress_all.21539604043420053864775214095437447790654841295181062499256342638964790615893
    Line 8704, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all/latest/run.log
```
  UVM_ERROR @  38216730 ps: (cip_base_vseq.sv:549) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  38216730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 44.aes_core_fi.50399677105739604177418711254037272424478988370599787343744488876962675784147
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008631575 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008631575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.75979252617865028711905090551822269356583665079757788397021305387731849192385
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10148417039 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb0e84384, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10148417039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```