AES/UNMASKED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	53.931us	1	1	100.00
V1	smoke	aes_smoke	5.000s	346.407us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	215.000us	5	5	100.00
V1	csr_rw	aes_csr_rw	12.000s	59.108us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.261ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	124.502us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	18.000s	301.110us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	12.000s	59.108us	20	20	100.00
		aes_csr_aliasing	9.000s	124.502us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	346.407us	50	50	100.00
		aes_config_error	7.000s	287.996us	50	50	100.00
		aes_stress	5.000s	250.692us	50	50	100.00
V2	key_length	aes_smoke	5.000s	346.407us	50	50	100.00
		aes_config_error	7.000s	287.996us	50	50	100.00
		aes_stress	5.000s	250.692us	50	50	100.00
V2	back2back	aes_stress	5.000s	250.692us	50	50	100.00
		aes_b2b	10.000s	134.354us	50	50	100.00
V2	backpressure	aes_stress	5.000s	250.692us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	346.407us	50	50	100.00
		aes_config_error	7.000s	287.996us	50	50	100.00
		aes_stress	5.000s	250.692us	50	50	100.00
		aes_alert_reset	9.000s	287.426us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	56.910us	50	50	100.00
		aes_config_error	7.000s	287.996us	50	50	100.00
		aes_alert_reset	9.000s	287.426us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	192.652us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	164.826us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	287.426us	50	50	100.00
V2	stress	aes_stress	5.000s	250.692us	50	50	100.00
V2	sideload	aes_stress	5.000s	250.692us	50	50	100.00
		aes_sideload	9.000s	242.542us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	182.639us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	604.083us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	228.427us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	180.288us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	180.288us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	215.000us	5	5	100.00
		aes_csr_rw	12.000s	59.108us	20	20	100.00
		aes_csr_aliasing	9.000s	124.502us	5	5	100.00
		aes_same_csr_outstanding	9.000s	418.289us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	215.000us	5	5	100.00
		aes_csr_rw	12.000s	59.108us	20	20	100.00
		aes_csr_aliasing	9.000s	124.502us	5	5	100.00
		aes_same_csr_outstanding	9.000s	418.289us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	325.055us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	340.161us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	2.416ms	5	5	100.00
		aes_tl_intg_err	15.000s	232.893us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	232.893us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	287.426us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	346.407us	50	50	100.00
		aes_stress	5.000s	250.692us	50	50	100.00
		aes_alert_reset	9.000s	287.426us	50	50	100.00
		aes_core_fi	6.767m	10.013ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	147.236us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	119.483us	50	50	100.00
		aes_stress	5.000s	250.692us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	250.692us	50	50	100.00
		aes_sideload	9.000s	242.542us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	119.483us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	119.483us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	119.483us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	119.483us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	119.483us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	250.692us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	250.692us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	93.668us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	93.668us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.003ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	93.668us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	287.426us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_ctr_fi	8.000s	109.529us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	93.668us	50	50	100.00
		aes_control_fi	49.000s	19.719ms	281	300	93.67
		aes_cipher_fi	48.000s	10.003ms	325	350	92.86
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.617m	38.829ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1545	1602	96.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.55	94.48	98.81	93.86	97.64	93.33	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_control_fi has 14 failures.
  - 3.aes_control_fi.80818818225807329852430311183979449210934111264257181191714912507832859595716
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:13665381-d3ca-44f6-aebc-fd65092ecbd6
```
  - 16.aes_control_fi.26362975224064093516157558614082239704606149600193198555156232708792844950989
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:3df975f4-8e35-4190-ac16-a63ed2e4f80e
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 12 failures.
  - 31.aes_cipher_fi.44283651261845441025423451972985563962382306179153108120887441691019614978748
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d094b4ba-8625-4ba7-91a9-7c1ead277153
```
  - 88.aes_cipher_fi.78896215887403225741963749786389658436972047197817537420095166695931139705636
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/88.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0a2e54df-7a77-49b8-a79a-504390ca788c
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 24.aes_cipher_fi.28619014172841621931374332525355320844901949128192285241877183814189841067109
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002885614 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002885614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_cipher_fi.6241146375861289247605728558646524572448913264166579901800853640421631432309
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021272734 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021272734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.57968956227358620371893950104590490174194768380804262131286214222443818176412
Line 645, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38829002578 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 38829002578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.55811641856032122368118721849107495100703275445452074256836680800265391719741
Line 948, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 866286915 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 866286915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 5.aes_control_fi.103719570759419123942863882746467700573732604469958987189715813305011259243690
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006366155 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006366155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 153.aes_control_fi.25092109909501432337301821982786078453810682382530466344538108834323040192009
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/153.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016092470 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016092470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.82738115715939131737855501417639291404459431270942793556437034569680233664635
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002496778 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002496778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.12015757876634658223734214262814080820922219210593545936602583544912094994270
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006988449 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006988449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.79952642052436398491025312306625114198540636098925817454105093852452439154515
Line 727, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 272760290 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 272760290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.81663527691905426306826967885714440367787325087494339868515633288150958179955
Line 610, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 562573577 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 562573577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.51327280727955618602016267528143170766003166074049394500256378556706434336736
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012977870 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x2e523584, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10012977870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```