AES/UNMASKED Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	58.682us	1	1	100.00
V1	smoke	aes_smoke	5.000s	178.456us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	110.265us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	68.788us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	321.339us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	1.078ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	130.911us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	68.788us	20	20	100.00
		aes_csr_aliasing	6.000s	1.078ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	178.456us	50	50	100.00
		aes_config_error	5.000s	121.668us	50	50	100.00
		aes_stress	5.000s	108.047us	50	50	100.00
V2	key_length	aes_smoke	5.000s	178.456us	50	50	100.00
		aes_config_error	5.000s	121.668us	50	50	100.00
		aes_stress	5.000s	108.047us	50	50	100.00
V2	back2back	aes_stress	5.000s	108.047us	50	50	100.00
		aes_b2b	10.000s	392.216us	50	50	100.00
V2	backpressure	aes_stress	5.000s	108.047us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	178.456us	50	50	100.00
		aes_config_error	5.000s	121.668us	50	50	100.00
		aes_stress	5.000s	108.047us	50	50	100.00
		aes_alert_reset	5.000s	173.980us	49	50	98.00
V2	failure_test	aes_man_cfg_err	4.000s	227.105us	50	50	100.00
		aes_config_error	5.000s	121.668us	50	50	100.00
		aes_alert_reset	5.000s	173.980us	49	50	98.00
V2	trigger_clear_test	aes_clear	6.000s	1.313ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	190.627us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	173.980us	49	50	98.00
V2	stress	aes_stress	5.000s	108.047us	50	50	100.00
V2	sideload	aes_stress	5.000s	108.047us	50	50	100.00
		aes_sideload	5.000s	214.675us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	147.831us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	3.999ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	140.014us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	183.368us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	183.368us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	110.265us	5	5	100.00
		aes_csr_rw	13.000s	68.788us	20	20	100.00
		aes_csr_aliasing	6.000s	1.078ms	5	5	100.00
		aes_same_csr_outstanding	10.000s	88.667us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	110.265us	5	5	100.00
		aes_csr_rw	13.000s	68.788us	20	20	100.00
		aes_csr_aliasing	6.000s	1.078ms	5	5	100.00
		aes_same_csr_outstanding	10.000s	88.667us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	6.000s	467.187us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	78.898us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	3.375ms	5	5	100.00
		aes_tl_intg_err	14.000s	133.606us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	133.606us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	173.980us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	178.456us	50	50	100.00
		aes_stress	5.000s	108.047us	50	50	100.00
		aes_alert_reset	5.000s	173.980us	49	50	98.00
		aes_core_fi	6.700m	10.011ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	55.267us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	51.056us	50	50	100.00
		aes_stress	5.000s	108.047us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	108.047us	50	50	100.00
		aes_sideload	5.000s	214.675us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	51.056us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	51.056us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	51.056us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	51.056us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	51.056us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	108.047us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	108.047us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	146.306us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	146.306us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.003ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	146.306us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	173.980us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_ctr_fi	4.000s	158.532us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	146.306us	48	50	96.00
		aes_control_fi	50.000s	25.038ms	280	300	93.33
		aes_cipher_fi	46.000s	10.003ms	323	350	92.29
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.900m	5.271ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.43	94.18	98.77	93.60	97.72	93.33	98.66	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_fi has 1 failures.
  - 0.aes_fi.15338203839845883787713336139037027477144797576913651632687454936951664255777
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_fi/latest/run.log
```
  Job ID: smart:be45e54d-6a50-4955-be63-fcc4105ca496
```
- Test aes_control_fi has 12 failures.
  - 0.aes_control_fi.91191574531281008087803938742634859449521931833662664531417917276086082667586
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:25764c04-d149-494d-9ec8-fc569eb28429
```
  - 2.aes_control_fi.104496050109185128686673437979315909520092331632963362495411955017342926605636
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job ID: smart:e450c3e6-9f98-497d-a8c1-facdc85152b0
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 15 failures.
  - 14.aes_cipher_fi.50568092858340929747758559165489194954234701369987573917144701788963304675587
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1cb57fae-eede-430b-a0d3-bec923e51ced
```
  - 44.aes_cipher_fi.80807470193232955397962114103472463452000900154883768134423562207075676169435
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  Job ID: smart:edee6039-fb65-42fc-bae5-f1236b5ed0d9
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 39.aes_cipher_fi.372372946597283605245593957926063157774783292600553131168014412731256059418
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011063304 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011063304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_cipher_fi.85971641503436516864568305748368493242497589206554048254068098174298692246154
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003379042 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003379042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 21.aes_control_fi.39950766345314097375388695865647290469974070734364683238342836547875739069881
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021410833 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021410833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_control_fi.70829748993823979950999009127990413073933071015431977887771583112648821548117
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003721084 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003721084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.89815096433287843274406666048849496388117812444142806113049653598898572113437
Line 685, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 296891971 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 296891971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.25273846881655491627073218363251147231134759982452329752454921858826776570831
Line 637, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 678788196 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 678788196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 6.aes_core_fi.51644584259010374089125086742178478176866514959047993578178482309694912775612
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005948166 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005948166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_core_fi.37777958150004604427842183603120001888172861653764871739935492580984729433468
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038087921 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038087921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.12558922816278290285249557629568152467479466425701989675990154876767172035725
Line 1827, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 538134833 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 538134833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.85991851059889862652584708078094468441891711875434502627278470591709996258393
Line 1405, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 394414037 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 394414037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 0.aes_core_fi.84065830931584718213545172393488117900496370551847156401883751249644749262279
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020646592 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x20ff1384, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10020646592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:549) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.90637494682985963964219424153253775308376721959090817058496205501773174982804
    Line 309, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  21800004 ps: (cip_base_vseq.sv:549) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  21800004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 13.aes_core_fi.1869401940671762748435339355660615873245636227104351186258722680320550703160
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010685433 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd3fd0684, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10010685433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

21.aes_alert_reset.49705087041425658317473431305327984628492536872998034705898135415224522425171
Line 4133, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 21715633 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21695225 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 21715633 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 21695225 PS)
  UVM_ERROR @  21715633 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 24.aes_fi.24159221047859750098321905085390760664797378568570932015125646110027089271450
    Line 2403, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 7014598 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 7004394 PS)
  UVM_ERROR @   7014598 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   7014598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```