AES/UNMASKED Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	63.880us	1	1	100.00
V1	smoke	aes_smoke	9.000s	60.311us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	13.000s	60.981us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	54.896us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	188.675us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	308.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	105.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	54.896us	20	20	100.00
		aes_csr_aliasing	8.000s	308.792us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	60.311us	50	50	100.00
		aes_config_error	14.000s	469.783us	50	50	100.00
		aes_stress	10.000s	167.264us	50	50	100.00
V2	key_length	aes_smoke	9.000s	60.311us	50	50	100.00
		aes_config_error	14.000s	469.783us	50	50	100.00
		aes_stress	10.000s	167.264us	50	50	100.00
V2	back2back	aes_stress	10.000s	167.264us	50	50	100.00
		aes_b2b	15.000s	1.602ms	50	50	100.00
V2	backpressure	aes_stress	10.000s	167.264us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	60.311us	50	50	100.00
		aes_config_error	14.000s	469.783us	50	50	100.00
		aes_stress	10.000s	167.264us	50	50	100.00
		aes_alert_reset	9.000s	116.087us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	63.056us	50	50	100.00
		aes_config_error	14.000s	469.783us	50	50	100.00
		aes_alert_reset	9.000s	116.087us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	186.729us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	383.767us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	116.087us	50	50	100.00
V2	stress	aes_stress	10.000s	167.264us	50	50	100.00
V2	sideload	aes_stress	10.000s	167.264us	50	50	100.00
		aes_sideload	8.000s	99.811us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	69.797us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	7.489ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	68.275us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	162.532us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	162.532us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	13.000s	60.981us	5	5	100.00
		aes_csr_rw	7.000s	54.896us	20	20	100.00
		aes_csr_aliasing	8.000s	308.792us	5	5	100.00
		aes_same_csr_outstanding	14.000s	350.141us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	13.000s	60.981us	5	5	100.00
		aes_csr_rw	7.000s	54.896us	20	20	100.00
		aes_csr_aliasing	8.000s	308.792us	5	5	100.00
		aes_same_csr_outstanding	14.000s	350.141us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	166.206us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	85.010us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	645.247us	5	5	100.00
		aes_tl_intg_err	10.000s	1.846ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	1.846ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	116.087us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	60.311us	50	50	100.00
		aes_stress	10.000s	167.264us	50	50	100.00
		aes_alert_reset	9.000s	116.087us	50	50	100.00
		aes_core_fi	3.150m	10.020ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	65.223us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	87.252us	50	50	100.00
		aes_stress	10.000s	167.264us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	167.264us	50	50	100.00
		aes_sideload	8.000s	99.811us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	87.252us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	87.252us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	87.252us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	87.252us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	87.252us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	167.264us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	167.264us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	95.331us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	95.331us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.004ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	95.331us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	116.087us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_ctr_fi	8.000s	49.706us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	95.331us	50	50	100.00
		aes_control_fi	49.000s	10.002ms	281	300	93.67
		aes_cipher_fi	52.000s	10.004ms	324	350	92.57
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	694.141us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.26	97.57	94.52	98.81	93.80	97.72	93.33	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_cipher_fi has 14 failures.
  - 4.aes_cipher_fi.58326918422096503101551543862060326224344103788862686299396237985225496704550
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8d94a41d-b4a0-4f90-976c-1b9afedc26cf
```
  - 22.aes_cipher_fi.79768862395516942180605164848271804216582254422071089483039289582472564712877
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ac1c2e35-14bb-4c65-bddf-b625308dbb89
```
  - ... and 12 more failures.
- Test aes_control_fi has 13 failures.
  - 22.aes_control_fi.87342660822447017828035467568956875331649130462102988890083690509161047620975
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:f15a1c93-57f7-48ca-a105-b1817c82ff12
```
  - 27.aes_control_fi.8196584995879751407065143144682173457813436984164388880311627616488011340384
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:fafeee5b-cea4-4d13-9209-d6c29e0ffcbb
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 33.aes_cipher_fi.12591898612103658878365056819753912283107836866274613138933564891785600270419
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005479072 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005479072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.aes_cipher_fi.98569967076838592617011331236743450205909267819411482828934556553515008882766
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007519023 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007519023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 14.aes_control_fi.41095399997306048550560624646447947197272342123646776402615556044224535686088
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009164589 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009164589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_control_fi.93627985672980149130783055042332991321728023682575141531567614950316435036305
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007807250 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007807250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.63792252250300849891962211492331162497098394490895879029549119670847859507562
Line 360, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  46848236 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  46848236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.25187478103729188844410389237547835242999348255137654848428113380055209210508
Line 653, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 250024709 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 250024709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.19476738376690094708728191488938462291403043681402219164818147112265164983686
    Line 1092, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 685244999 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 685244999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.31863908495126877884629874017789865901903264397384862089430205986307273050968
    Line 539, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 391587500 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 391587500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.68017228642115082403767287370190205121319491152652963926120871466093601114296
    Line 1050, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1215124821 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1215124821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_stress_all_with_rand_reset.10127907986614355898948771303502823705979323049252084864322907299450192407357
    Line 685, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3005692575 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3005692575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 29.aes_core_fi.25505798744596729433536649585367069984014604066946556691939721606620091346574
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008260561 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008260561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.57764641036203852171259368959103278700229977682031697346440629267656975383991
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004701955 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004701955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.66240944270115314316279271119455029031299782172305649441651941398305400813707
    Line 1319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 694140752 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 694140752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 24.aes_core_fi.78793521625657245035094589835763298431932130124268874026793347546679333189137
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051111447 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051111447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.67677449360868917065811204571862667738417369270727620377007113320455109449312
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019909126 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x90cec284, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10019909126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```