AES/UNMASKED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	60.179us	1	1	100.00
V1	smoke	aes_smoke	6.000s	156.494us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	51.792us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	79.912us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	510.569us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	224.101us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	181.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	79.912us	20	20	100.00
		aes_csr_aliasing	4.000s	224.101us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	156.494us	50	50	100.00
		aes_config_error	11.000s	359.214us	50	50	100.00
		aes_stress	5.000s	159.981us	50	50	100.00
V2	key_length	aes_smoke	6.000s	156.494us	50	50	100.00
		aes_config_error	11.000s	359.214us	50	50	100.00
		aes_stress	5.000s	159.981us	50	50	100.00
V2	back2back	aes_stress	5.000s	159.981us	50	50	100.00
		aes_b2b	10.000s	238.458us	50	50	100.00
V2	backpressure	aes_stress	5.000s	159.981us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	156.494us	50	50	100.00
		aes_config_error	11.000s	359.214us	50	50	100.00
		aes_stress	5.000s	159.981us	50	50	100.00
		aes_alert_reset	10.000s	752.707us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	57.006us	50	50	100.00
		aes_config_error	11.000s	359.214us	50	50	100.00
		aes_alert_reset	10.000s	752.707us	50	50	100.00
V2	trigger_clear_test	aes_clear	5.000s	85.831us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	173.550us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	752.707us	50	50	100.00
V2	stress	aes_stress	5.000s	159.981us	50	50	100.00
V2	sideload	aes_stress	5.000s	159.981us	50	50	100.00
		aes_sideload	7.000s	214.792us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	79.991us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	2.919ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	81.877us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	79.201us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	79.201us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	51.792us	5	5	100.00
		aes_csr_rw	3.000s	79.912us	20	20	100.00
		aes_csr_aliasing	4.000s	224.101us	5	5	100.00
		aes_same_csr_outstanding	8.000s	180.639us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	51.792us	5	5	100.00
		aes_csr_rw	3.000s	79.912us	20	20	100.00
		aes_csr_aliasing	4.000s	224.101us	5	5	100.00
		aes_same_csr_outstanding	8.000s	180.639us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	82.795us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	395.583us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	826.408us	5	5	100.00
		aes_tl_intg_err	5.000s	225.915us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	225.915us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	752.707us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	156.494us	50	50	100.00
		aes_stress	5.000s	159.981us	50	50	100.00
		aes_alert_reset	10.000s	752.707us	50	50	100.00
		aes_core_fi	1.100m	10.056ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	116.735us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	79.901us	50	50	100.00
		aes_stress	5.000s	159.981us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	159.981us	50	50	100.00
		aes_sideload	7.000s	214.792us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	79.901us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	79.901us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	79.901us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	79.901us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	79.901us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	159.981us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	159.981us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	123.884us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	123.884us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	32.843ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	123.884us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	752.707us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_ctr_fi	8.000s	68.306us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	123.884us	48	50	96.00
		aes_control_fi	44.000s	32.839ms	279	300	93.00
		aes_cipher_fi	48.000s	32.843ms	322	350	92.00
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.433m	7.297ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.55	94.48	98.81	93.71	97.72	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_control_fi has 15 failures.
  - 26.aes_control_fi.100105195091079460585548473873670337821175582454271198994353580920251034165631
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:302a82bc-6a8b-487f-91d7-d1c9faaf50b8
```
  - 43.aes_control_fi.108263548620329754235841908688535396750750512833175074577797493159336075150747
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:fdec609e-c68e-4c9b-aab2-9ad7bc9a902d
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 18 failures.
  - 27.aes_cipher_fi.104807208025407011414888683299856963481042403689776932649267539441554982394692
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c90d81e7-b49c-4f5f-bb4a-99bbe9f84b65
```
  - 29.aes_cipher_fi.102631308546074963703489418627548094706974543923521337705883911076621124338273
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b37d2e29-e8e1-487d-9c48-b200c9f6cc00
```
  - ... and 16 more failures.
- Test aes_fi has 1 failures.
  - 46.aes_fi.96784016110831872045658124551603612287945275533591301623004750646079595706857
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log
```
  Job ID: smart:582fd207-992f-4d23-8fe8-2f8e49b03b8a
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 43.aes_cipher_fi.48822410585528535499493234904678489595087986541820544591337990212337001353920
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004597281 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004597281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_cipher_fi.63166627671463208845071353189321521895862647641198054016367135043027535123429
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002947788 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002947788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.113436808218077220049771603503540216901169871828098934904225847416164376943293
Line 466, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6901929068 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6901929068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.103715973912515696621983962058110207569353968634632367570008410167462575057400
Line 1363, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2047994240 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2047994240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 74.aes_control_fi.107230857270066200425499705540304785764042710666130647236471023350542776415871
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003521706 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003521706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 104.aes_control_fi.69598982383984842676926910757883885169672001290911917873791501756701433890635
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/104.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015770089 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015770089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.12015739073487793007671695974590781963832759684819843218932046154095368011272
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011028975 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011028975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.100882483279543846398050019127378776870203181788422193342609319266008027304441
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012372101 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012372101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 6.aes_core_fi.39372249202823858067879734894049315556407018237984392730357826442248606312101
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10055897866 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5ce8684, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10055897866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.61717791455650926483280726447245571328470531331820506265197265642513946211016
    Line 475, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7296655367 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7296655367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

39.aes_fi.96110381138882417488605266676921457336659927804079171814590660754332315284771
Line 3845, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 31381691 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 31351388 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 31381691 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 31351388 PS)
  UVM_ERROR @  31381691 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut