AES/UNMASKED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	57.274us	1	1	100.00
V1	smoke	aes_smoke	14.000s	68.926us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	66.609us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	114.356us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	864.591us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	228.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	136.717us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	114.356us	20	20	100.00
		aes_csr_aliasing	5.000s	228.883us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	68.926us	50	50	100.00
		aes_config_error	9.000s	462.093us	50	50	100.00
		aes_stress	23.000s	134.702us	50	50	100.00
V2	key_length	aes_smoke	14.000s	68.926us	50	50	100.00
		aes_config_error	9.000s	462.093us	50	50	100.00
		aes_stress	23.000s	134.702us	50	50	100.00
V2	back2back	aes_stress	23.000s	134.702us	50	50	100.00
		aes_b2b	18.000s	325.310us	50	50	100.00
V2	backpressure	aes_stress	23.000s	134.702us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	68.926us	50	50	100.00
		aes_config_error	9.000s	462.093us	50	50	100.00
		aes_stress	23.000s	134.702us	50	50	100.00
		aes_alert_reset	8.000s	122.893us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	53.859us	50	50	100.00
		aes_config_error	9.000s	462.093us	50	50	100.00
		aes_alert_reset	8.000s	122.893us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	80.412us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	1.056ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	122.893us	50	50	100.00
V2	stress	aes_stress	23.000s	134.702us	50	50	100.00
V2	sideload	aes_stress	23.000s	134.702us	50	50	100.00
		aes_sideload	14.000s	189.319us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	64.766us	50	50	100.00
V2	stress_all	aes_stress_all	38.000s	932.467us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	71.348us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	268.628us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	268.628us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	66.609us	5	5	100.00
		aes_csr_rw	3.000s	114.356us	20	20	100.00
		aes_csr_aliasing	5.000s	228.883us	5	5	100.00
		aes_same_csr_outstanding	4.000s	68.561us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	66.609us	5	5	100.00
		aes_csr_rw	3.000s	114.356us	20	20	100.00
		aes_csr_aliasing	5.000s	228.883us	5	5	100.00
		aes_same_csr_outstanding	4.000s	68.561us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	15.000s	477.730us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	124.627us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.211ms	5	5	100.00
		aes_tl_intg_err	5.000s	569.565us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	569.565us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	122.893us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	68.926us	50	50	100.00
		aes_stress	23.000s	134.702us	50	50	100.00
		aes_alert_reset	8.000s	122.893us	50	50	100.00
		aes_core_fi	1.617m	10.044ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	59.212us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	82.046us	50	50	100.00
		aes_stress	23.000s	134.702us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	23.000s	134.702us	50	50	100.00
		aes_sideload	14.000s	189.319us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	82.046us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	82.046us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	82.046us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	82.046us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	82.046us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	23.000s	134.702us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	23.000s	134.702us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	190.526us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	190.526us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.011ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	190.526us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	122.893us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_ctr_fi	13.000s	56.366us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	190.526us	50	50	100.00
		aes_control_fi	49.000s	65.622ms	281	300	93.67
		aes_cipher_fi	48.000s	10.011ms	327	350	93.43
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	28.000s	1.919ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.04	97.37	94.05	98.71	93.34	97.72	91.11	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 14 failures.
  - 1.aes_cipher_fi.52723169108064948291452765480082637326314439978870036979470742228768776390400
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4c80fd73-2eba-4fc0-8e19-06cedd0ae6ce
```
  - 14.aes_cipher_fi.38289554036293673301656267716847735655704637882822066715631112587924385398270
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:efa9967f-83c2-4aba-98bb-874e2e12ba4b
```
  - ... and 12 more failures.
- Test aes_control_fi has 15 failures.
  - 18.aes_control_fi.106459733455014903292047971169487728540081035610259471727941137054042178363151
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:29503664-c8b5-48d5-a2f7-63131e162ae7
```
  - 35.aes_control_fi.53560530871894129595293469492093953704333524486140497994656920452723280696067
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:445a59fa-40a8-4cc4-bfe5-0842b721a4e8
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 24.aes_cipher_fi.90931861380015444278520039732107128206535594648892192340475797640581329829517
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004440989 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004440989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_cipher_fi.67262390086177829305291911162000636623187417307678070870189386171251019590031
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010546894 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010546894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 49.aes_control_fi.99895961213372529496036162010478425984623178167289608591642212599044093229129
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009381494 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009381494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 120.aes_control_fi.86662964658345596338297160869344661971930679474279405892704376822855301787777
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/120.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010418816 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010418816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.30505439173284606363762947956085218236415248901794702416071841180757181059418
Line 780, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 170962268 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 170962268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.56626288902581732915066098066654595395398108146139815469548567661700762336684
Line 1121, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1616782361 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1616782361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 6.aes_stress_all_with_rand_reset.23192901283449304091732066450985747087226025589643613419109446200992633216701
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  37530257 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  37530257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_stress_all_with_rand_reset.62666065236116846375443658439574012539147328163134309311409259677783277951373
    Line 335, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  93732358 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  93732358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.44579785467873471123786639672536635738954410540388937714479253294472088509994
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  22010125 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  22010125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_stress_all_with_rand_reset.86636799964767878474172087626136087520138685103043680558974352364013493719736
    Line 549, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 205855584 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 205855584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

5.aes_stress_all_with_rand_reset.98272551511217325258254589306419926388717504854387269645264772587175599767457
Line 825, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 205239763 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 205239763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.58212577648177125403529655919848505343094256141361224883461521355835784125558
Line 1264, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1919068021 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1919068021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 16.aes_core_fi.39466199194317919413618778597780057593138016810248900606019161549011971971939
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016262532 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016262532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_core_fi.60871819311556385117331745695597676284104546980967144611900796849864766358143
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022607253 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022607253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.113083961797880669158810794734256221183597234791898964758839621278394867933900
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026392980 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026392980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 54.aes_core_fi.31153709357207309526549523331630135860545557157867599684783343954987332607686
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10044164247 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xba23f984, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10044164247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```