AES/UNMASKED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	62.158us	1	1	100.00
V1	smoke	aes_smoke	14.000s	56.799us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	52.040us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	66.133us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	861.992us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	223.830us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	62.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	66.133us	20	20	100.00
		aes_csr_aliasing	4.000s	223.830us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	56.799us	50	50	100.00
		aes_config_error	14.000s	63.195us	50	50	100.00
		aes_stress	9.000s	143.143us	50	50	100.00
V2	key_length	aes_smoke	14.000s	56.799us	50	50	100.00
		aes_config_error	14.000s	63.195us	50	50	100.00
		aes_stress	9.000s	143.143us	50	50	100.00
V2	back2back	aes_stress	9.000s	143.143us	50	50	100.00
		aes_b2b	13.000s	87.183us	50	50	100.00
V2	backpressure	aes_stress	9.000s	143.143us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	56.799us	50	50	100.00
		aes_config_error	14.000s	63.195us	50	50	100.00
		aes_stress	9.000s	143.143us	50	50	100.00
		aes_alert_reset	13.000s	215.424us	50	50	100.00
V2	failure_test	aes_man_cfg_err	23.000s	62.754us	50	50	100.00
		aes_config_error	14.000s	63.195us	50	50	100.00
		aes_alert_reset	13.000s	215.424us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	70.046us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	374.519us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	215.424us	50	50	100.00
V2	stress	aes_stress	9.000s	143.143us	50	50	100.00
V2	sideload	aes_stress	9.000s	143.143us	50	50	100.00
		aes_sideload	14.000s	92.070us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	172.231us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	1.827ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	141.783us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	181.232us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	181.232us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	52.040us	5	5	100.00
		aes_csr_rw	3.000s	66.133us	20	20	100.00
		aes_csr_aliasing	4.000s	223.830us	5	5	100.00
		aes_same_csr_outstanding	4.000s	108.716us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	52.040us	5	5	100.00
		aes_csr_rw	3.000s	66.133us	20	20	100.00
		aes_csr_aliasing	4.000s	223.830us	5	5	100.00
		aes_same_csr_outstanding	4.000s	108.716us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	15.000s	94.543us	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	327.941us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.269ms	5	5	100.00
		aes_tl_intg_err	5.000s	768.701us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	768.701us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	215.424us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	56.799us	50	50	100.00
		aes_stress	9.000s	143.143us	50	50	100.00
		aes_alert_reset	13.000s	215.424us	50	50	100.00
		aes_core_fi	43.000s	10.106ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	115.666us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	79.972us	50	50	100.00
		aes_stress	9.000s	143.143us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	143.143us	50	50	100.00
		aes_sideload	14.000s	92.070us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	79.972us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	79.972us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	79.972us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	79.972us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	79.972us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	143.143us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	143.143us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	224.491us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	224.491us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	32.162ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	224.491us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	215.424us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_ctr_fi	16.000s	52.559us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	224.491us	50	50	100.00
		aes_control_fi	50.000s	71.577ms	275	300	91.67
		aes_cipher_fi	49.000s	32.162ms	330	350	94.29
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	27.000s	509.019us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.55	94.48	98.81	93.74	97.72	93.33	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 14 failures.
  - 13.aes_control_fi.43493704748193932725392714522791366496119642919262565491712744042939973739028
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:4c84d5f3-06b2-4106-9d57-04b5b9a5ccae
```
  - 18.aes_control_fi.103465636172806493965376633817936812149663268532023835831881721157271603107576
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:023ad589-ab51-4f6e-b95c-2d50cc016918
```
  - ... and 12 more failures.
- Test aes_ctr_fi has 1 failures.
  - 42.aes_ctr_fi.87446651332061393800046653545227488293207889547496792123554228252853926314475
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_ctr_fi/latest/run.log
```
  Job ID: smart:61430b01-34ff-4222-8540-b3107d33b593
```
- Test aes_cipher_fi has 10 failures.
  - 45.aes_cipher_fi.11488742502931530071311492890151919784604355174397109755268848731744677090101
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7aca962e-405b-452e-b497-0fc11d7fa777
```
  - 94.aes_cipher_fi.78932950746661204563626909823212732067643145543750243469026487856420620966682
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/94.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dd731f1b-937d-46dc-b8db-6c05b5049eef
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 3.aes_cipher_fi.54761761509987204463345977162364501408398641911647323968808388265572859127494
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005642207 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005642207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.aes_cipher_fi.61357339079016059192709215366556603306702007675945646060463876934757125054996
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036686621 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036686621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 27.aes_control_fi.12507721245291857307357189044088984336138734043739018981153844605232379256974
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014457298 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014457298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 103.aes_control_fi.63181254777161837621765271293085572016730728399834907693864655093510380471940
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009651141 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009651141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 4.aes_core_fi.99909888805929766063732334967579872413175365797161240202467468765447700815584
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013045006 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013045006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_core_fi.104663991944530694163178976294702404218575501375280822339901306890604845006287
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006786295 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006786295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.65021998779789315640796639065762336958363581487101787913341544465082217536610
Line 711, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1029317375 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1029317375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.31309947167879364172327031844285069284170567367115360688739067924448847160657
Line 1101, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 508387861 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 508387861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.82587991567028531991261092952142184311712159604542592992664110127999813521542
Line 1688, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 509019210 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 509019210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.109416030109990218628732864204029255616818700046156324052412069767898908045338
Line 1515, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1738767272 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1738767272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.38203051998881103656161540262335122896831355587958707926444016250487769897659
    Line 336, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  54886461 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  54886461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.55998664602682009098377313142656152564169132184306106972584888162250307660153
    Line 725, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1025359015 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1025359015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_control_fi has 1 failures.
  - 0.aes_control_fi.36576293843334890233930180667103653144671423718125364694439233333390032094116
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_ERROR @  27893993 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  27893993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 1.aes_stress_all.97931424751152155278059679933541826998831819232544617604959386921845597508218
    Line 37642, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 1282728568 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 1282728568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.4472695361493104438945574916686130576586183535997049904951031347387462523539
    Line 1272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3640108394 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3640108394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.104036107491104255560601254064239809000852744884589300746681658463427779272199
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  52342381 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  52342381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.111415757886654473519863316176367944659250219849948796657085695467359215659877
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015726522 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015726522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 36.aes_core_fi.38237630196311537572729145554092898981756087119214516157241696722115654182954
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10106171699 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xdd661384, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10106171699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```