AES/UNMASKED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	84.320us	1	1	100.00
V1	smoke	aes_smoke	13.000s	54.810us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	63.212us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	77.861us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.507ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	163.215us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	169.184us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	77.861us	20	20	100.00
		aes_csr_aliasing	5.000s	163.215us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	54.810us	50	50	100.00
		aes_config_error	6.000s	203.623us	50	50	100.00
		aes_stress	6.000s	95.581us	50	50	100.00
V2	key_length	aes_smoke	13.000s	54.810us	50	50	100.00
		aes_config_error	6.000s	203.623us	50	50	100.00
		aes_stress	6.000s	95.581us	50	50	100.00
V2	back2back	aes_stress	6.000s	95.581us	50	50	100.00
		aes_b2b	11.000s	100.833us	50	50	100.00
V2	backpressure	aes_stress	6.000s	95.581us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	54.810us	50	50	100.00
		aes_config_error	6.000s	203.623us	50	50	100.00
		aes_stress	6.000s	95.581us	50	50	100.00
		aes_alert_reset	5.000s	123.819us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	61.801us	50	50	100.00
		aes_config_error	6.000s	203.623us	50	50	100.00
		aes_alert_reset	5.000s	123.819us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	64.783us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	723.402us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	123.819us	50	50	100.00
V2	stress	aes_stress	6.000s	95.581us	50	50	100.00
V2	sideload	aes_stress	6.000s	95.581us	50	50	100.00
		aes_sideload	9.000s	80.603us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	93.930us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	2.638ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	65.169us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	181.413us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	181.413us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	63.212us	5	5	100.00
		aes_csr_rw	3.000s	77.861us	20	20	100.00
		aes_csr_aliasing	5.000s	163.215us	5	5	100.00
		aes_same_csr_outstanding	4.000s	100.186us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	63.212us	5	5	100.00
		aes_csr_rw	3.000s	77.861us	20	20	100.00
		aes_csr_aliasing	5.000s	163.215us	5	5	100.00
		aes_same_csr_outstanding	4.000s	100.186us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	821.179us	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	87.912us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	807.629us	5	5	100.00
		aes_tl_intg_err	5.000s	140.085us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	140.085us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	123.819us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	54.810us	50	50	100.00
		aes_stress	6.000s	95.581us	50	50	100.00
		aes_alert_reset	5.000s	123.819us	50	50	100.00
		aes_core_fi	6.250m	10.009ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	87.263us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	279.341us	50	50	100.00
		aes_stress	6.000s	95.581us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	95.581us	50	50	100.00
		aes_sideload	9.000s	80.603us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	279.341us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	279.341us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	279.341us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	279.341us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	279.341us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	95.581us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	95.581us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	286.017us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	286.017us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.002ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	286.017us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	123.819us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_ctr_fi	8.000s	53.793us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	286.017us	50	50	100.00
		aes_control_fi	51.000s	104.974ms	279	300	93.00
		aes_cipher_fi	47.000s	10.002ms	323	350	92.29
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	41.000s	11.399ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.48	94.31	98.81	93.65	97.64	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 11 failures.
  - 22.aes_control_fi.16635793548718855726523782917930577550385952459237707857977559292207709932051
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:90a154b4-525b-4fc0-8fa3-3795de2df6ed
```
  - 35.aes_control_fi.72156225014167875612532340347269309300302314793836102512865494739851047839788
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:b7c7d9e2-f671-441f-880d-bcd252965243
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 13 failures.
  - 97.aes_cipher_fi.42321145286893807391340626055975779746490468597528001566653421507054626337154
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/97.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d0d81e03-d624-4622-90f0-f36d122f5272
```
  - 115.aes_cipher_fi.106469618326551282089915724475025077728656096801615245939386226336261703857221
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/115.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ac55931f-cd51-4c41-a576-13550dae02ed
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 54.aes_cipher_fi.65138942965224731875427184667826100616471006683293412430360492045566673688019
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002891167 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002891167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 76.aes_cipher_fi.54189873550793660099337694489490105168774240571008900802362695032163107241433
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006187650 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006187650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 3.aes_control_fi.28510543180688249380499398752153534192892391931177442517686724961585265910792
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007725894 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007725894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_control_fi.111407263452929711852879151799364090219556166956628490115354557666791627900064
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022462422 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022462422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.21893858873524046350855453973652641485091670955014482322369686270178923558532
Line 1548, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3527868815 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3527868815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.105569483069120923719742247445487588401542586459495139897532976756784653980895
Line 658, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 282471936 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 282471936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 14.aes_core_fi.28521151670091641632939897749916589498980476548269250153901781693185459626884
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003306912 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003306912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.aes_core_fi.50453881609609177992856838533406613871557724357535480890708076038000609432513
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002757347 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002757347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.27771524193376606132281342829635087889460164886398918579117002430443872626962
    Line 340, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  66952536 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  66952536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.5339632728473040813374790460836690409681039147903684300170818803489920667984
    Line 834, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 195835672 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 195835672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.49412946743853611721538309194997539407595052774915681691474916840074456823441
    Line 1250, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1295725333 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1295725333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 8.aes_core_fi.9472354447059425532794400607058052442923211408687967501282540875067402296924
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018083146 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd1f5f684, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10018083146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.104564152194181785624477780005469382447698303272264430638533243557020839526419
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  37104556 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  37104556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 24.aes_core_fi.107558206637794491819639065112362037350405868749301408103814934961899638152077
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008724440 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x29dc3384, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10008724440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```