AES/UNMASKED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	65.918us	1	1	100.00
V1	smoke	aes_smoke	9.000s	108.072us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.162us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	126.339us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	321.314us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	14.000s	89.334us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	85.944us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	126.339us	20	20	100.00
		aes_csr_aliasing	14.000s	89.334us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	108.072us	50	50	100.00
		aes_config_error	8.000s	105.572us	50	50	100.00
		aes_stress	9.000s	245.282us	50	50	100.00
V2	key_length	aes_smoke	9.000s	108.072us	50	50	100.00
		aes_config_error	8.000s	105.572us	50	50	100.00
		aes_stress	9.000s	245.282us	50	50	100.00
V2	back2back	aes_stress	9.000s	245.282us	50	50	100.00
		aes_b2b	14.000s	214.635us	50	50	100.00
V2	backpressure	aes_stress	9.000s	245.282us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	108.072us	50	50	100.00
		aes_config_error	8.000s	105.572us	50	50	100.00
		aes_stress	9.000s	245.282us	50	50	100.00
		aes_alert_reset	14.000s	107.142us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	60.641us	50	50	100.00
		aes_config_error	8.000s	105.572us	50	50	100.00
		aes_alert_reset	14.000s	107.142us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	127.222us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	3.172ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	107.142us	50	50	100.00
V2	stress	aes_stress	9.000s	245.282us	50	50	100.00
V2	sideload	aes_stress	9.000s	245.282us	50	50	100.00
		aes_sideload	9.000s	316.922us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	482.522us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	4.085ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	52.980us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	215.219us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	215.219us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.162us	5	5	100.00
		aes_csr_rw	13.000s	126.339us	20	20	100.00
		aes_csr_aliasing	14.000s	89.334us	5	5	100.00
		aes_same_csr_outstanding	18.000s	280.996us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.162us	5	5	100.00
		aes_csr_rw	13.000s	126.339us	20	20	100.00
		aes_csr_aliasing	14.000s	89.334us	5	5	100.00
		aes_same_csr_outstanding	18.000s	280.996us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	386.908us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	161.121us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.272ms	5	5	100.00
		aes_tl_intg_err	5.000s	368.179us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	368.179us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	107.142us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	108.072us	50	50	100.00
		aes_stress	9.000s	245.282us	50	50	100.00
		aes_alert_reset	14.000s	107.142us	50	50	100.00
		aes_core_fi	27.000s	10.007ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	83.384us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	56.242us	50	50	100.00
		aes_stress	9.000s	245.282us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	245.282us	50	50	100.00
		aes_sideload	9.000s	316.922us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	56.242us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	56.242us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	56.242us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	56.242us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	56.242us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	245.282us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	245.282us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	128.267us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	128.267us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	128.267us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	107.142us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_ctr_fi	8.000s	47.214us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	128.267us	49	50	98.00
		aes_control_fi	46.000s	32.825ms	277	300	92.33
		aes_cipher_fi	48.000s	10.002ms	318	350	90.86
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	33.000s	1.356ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.52	94.39	98.77	93.77	97.72	93.33	98.66	97.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_control_fi has 11 failures.
  - 13.aes_control_fi.40331420614248213834675173881568995346615281096916300332769204845550430730486
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:a86a123d-5f2b-4aa0-bee8-4b97ddae5951
```
  - 16.aes_control_fi.31789781428211330446890979947960240839147408536193099430637484442410347503375
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:b1e81db3-d69a-4b9f-b90f-c58f4b1fcdb4
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 20 failures.
  - 18.aes_cipher_fi.56561131203031583108118437724801590562643467930072812689223708669336432226089
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dea7e760-1f64-4726-8812-b79dd90334c8
```
  - 57.aes_cipher_fi.88912774950088601704843845057929611053544956786573781180437357434160692708133
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b12e6656-103c-4487-a1f6-3d1740118744
```
  - ... and 18 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 52.aes_control_fi.29652272849642771001377617675283798368580954011962226984853085125904390857050
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017649267 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017649267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 74.aes_control_fi.40544605118134226866363197292944758339505887290254444357646886102070833662064
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011555646 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011555646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 66.aes_cipher_fi.97412976792948117123466646759122373781981918931058494950109958408412744102321
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10037168710 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037168710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 77.aes_cipher_fi.105476012492880727315323871170704489069906757835067973384934377762193171106300
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/77.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005666912 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005666912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.30806654280853499937794849526050557582880458575903424182430866189175436662650
Line 701, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 305204838 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 305204838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.55159440827068048284203663428930771832390654326693614385016763993887521253233
Line 1017, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 258207587 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 258207587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.34979361763020290988453631631626271590420687991232712992611982860777870385033
Line 386, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 268527158 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 268527158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.53688392234976189287994019097527226710993305869483371735509246497800587709517
Line 345, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  59198073 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  59198073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 61.aes_core_fi.82425070396215090664164663536271523666346367727753164171364996356486891373208
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007453789 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007453789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_core_fi.100003156679601044604884645606944813254436951339004765442740382200541529826220
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006565498 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006565498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.29102511361397023372430210609532955156925804334056372138397190637246301508575
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  19372867 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  19372867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.22260718492633616384652594189510619436493045838812465130107164642224980487710
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  36520476 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  36520476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 4.aes_fi.65576703870484180349869096150653626175725065176890342457297714487076662595669
    Line 7701, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_fi/latest/run.log
```
  UVM_FATAL @  24701639 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  24701639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.9939641752049415117032686106103032563679660289221393765306598939226500362482
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 119109263 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 119109263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```