AON_TIMER Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.390s	562.663us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.510s	1.376ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.250s	448.152us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.010s	6.095ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.690s	615.561us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	989.314us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.250s	448.152us	20	20	100.00
		aon_timer_csr_aliasing	1.690s	615.561us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.120s	448.321us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.130s	432.764us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.599m	59.269ms	50	50	100.00
V2	jump	aon_timer_jump	1.550s	538.881us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.508m	483.560ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.260s	517.164us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.060s	595.950us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.060s	595.950us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.510s	1.376ms	5	5	100.00
		aon_timer_csr_rw	1.250s	448.152us	20	20	100.00
		aon_timer_csr_aliasing	1.690s	615.561us	5	5	100.00
		aon_timer_same_csr_outstanding	5.100s	2.049ms	17	20	85.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.510s	1.376ms	5	5	100.00
		aon_timer_csr_rw	1.250s	448.152us	20	20	100.00
		aon_timer_csr_aliasing	1.690s	615.561us	5	5	100.00
		aon_timer_same_csr_outstanding	5.100s	2.049ms	17	20	85.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	11.040s	7.562ms	5	5	100.00
		aon_timer_tl_intg_err	14.010s	8.229ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.010s	8.229ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	13.559m	77.703ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 3 failures:

Test aon_timer_same_csr_outstanding has 3 failures.

5.aon_timer_same_csr_outstanding.1288934928
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 672072218 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 672072218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_same_csr_outstanding.2140979895
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 916243434 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 916243434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 31.aon_timer_stress_all.1071464147
    Line 240, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 19832858141 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 19832858141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```