748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.470s | 547.278us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.690s | 856.710us | 4 | 5 | 80.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.420s | 543.074us | 16 | 20 | 80.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 16.520s | 5.977ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.230s | 453.290us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.550s | 622.004us | 14 | 20 | 70.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.420s | 543.074us | 16 | 20 | 80.00 |
| aon_timer_csr_aliasing | 1.230s | 453.290us | 4 | 5 | 80.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.160s | 498.750us | 3 | 5 | 60.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.980s | 318.465us | 2 | 5 | 40.00 |
| V1 | TOTAL | 97 | 115 | 84.35 | |||
| V2 | prescaler | aon_timer_prescaler | 1.554m | 58.907ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.580s | 611.592us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 6.105m | 508.201ms | 49 | 50 | 98.00 |
| V2 | intr_test | aon_timer_intr_test | 1.360s | 471.014us | 46 | 50 | 92.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.400s | 364.059us | 16 | 20 | 80.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.400s | 364.059us | 16 | 20 | 80.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.690s | 856.710us | 4 | 5 | 80.00 |
| aon_timer_csr_rw | 1.420s | 543.074us | 16 | 20 | 80.00 | ||
| aon_timer_csr_aliasing | 1.230s | 453.290us | 4 | 5 | 80.00 | ||
| aon_timer_same_csr_outstanding | 3.430s | 2.388ms | 14 | 20 | 70.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.690s | 856.710us | 4 | 5 | 80.00 |
| aon_timer_csr_rw | 1.420s | 543.074us | 16 | 20 | 80.00 | ||
| aon_timer_csr_aliasing | 1.230s | 453.290us | 4 | 5 | 80.00 | ||
| aon_timer_same_csr_outstanding | 3.430s | 2.388ms | 14 | 20 | 70.00 | ||
| V2 | TOTAL | 225 | 240 | 93.75 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 10.560s | 8.090ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 13.980s | 8.534ms | 16 | 20 | 80.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 13.980s | 8.534ms | 16 | 20 | 80.00 |
| V2S | TOTAL | 21 | 25 | 84.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 15.769m | 357.570ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 393 | 430 | 91.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 1 | 12.50 |
| V2 | 6 | 6 | 2 | 33.33 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.56 | 99.82 | 95.32 | 100.00 | -- | 99.35 | 100.00 | 96.90 |
Exit reason: Error: User command failed Job returned non-zero exit code has 36 failures:
Test aon_timer_mem_partial_access has 3 failures.
0.aon_timer_mem_partial_access.31072908024982626745934598975445552703341969551789085272420707389032356815769
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_mem_partial_access/latest && /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515023769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.515023769
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.aon_timer_mem_partial_access.46753058667696421497261198970704934258434406912027005358616184753173368820000
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest/run.log
[make]: simulate
cd /workspace/1.aon_timer_mem_partial_access/latest && /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280701216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.4280701216
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test aon_timer_csr_bit_bash has 1 failures.
0.aon_timer_csr_bit_bash.36566871971682762082219273558925754842089708493440208520437497377687066624149
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347300501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3347300501
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test aon_timer_same_csr_outstanding has 6 failures.
0.aon_timer_same_csr_outstanding.100167657261987707218165791181816976437793858099382156801017745559053186594499
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169627331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.4169627331
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.aon_timer_same_csr_outstanding.54607764581469379982730545202404934435699595184519527445097649165163358812380
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/2.aon_timer_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43219164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.43219164
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
Test aon_timer_mem_walk has 2 failures.
1.aon_timer_mem_walk.57623631306137920366499195060683497369035781858507156222088946991066735340529
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest/run.log
[make]: simulate
cd /workspace/1.aon_timer_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197108209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.1197108209
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.aon_timer_mem_walk.54011146595889879290406525260881357526153377840055908731213965289288848222682
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest/run.log
[make]: simulate
cd /workspace/2.aon_timer_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281206746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.1281206746
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test aon_timer_csr_aliasing has 1 failures.
1.aon_timer_csr_aliasing.7803676384393741560798222723378954218789146400481600511881840883927280600353
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/1.aon_timer_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077129505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.3077129505
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more tests.
UVM_ERROR (aon_timer_scoreboard.sv:315) [scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (* [*] vs * [*]) has 1 failures:
24.aon_timer_stress_all.97340146778025388337191991532117464870872520915966049909714862565064098929242
Line 267, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all/latest/run.log
UVM_ERROR @ 14557366403 ps: (aon_timer_scoreboard.sv:315) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
UVM_INFO @ 14557366403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---