042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.430s | 562.076us | 37 | 50 | 74.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.660s | 726.127us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.260s | 497.175us | 14 | 20 | 70.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 16.770s | 11.767ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.630s | 696.319us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.520s | 561.261us | 11 | 20 | 55.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.260s | 497.175us | 14 | 20 | 70.00 |
| aon_timer_csr_aliasing | 1.630s | 696.319us | 4 | 5 | 80.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.680s | 488.906us | 2 | 5 | 40.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.190s | 507.843us | 4 | 5 | 80.00 |
| V1 | TOTAL | 81 | 115 | 70.43 | |||
| V2 | prescaler | aon_timer_prescaler | 1.451m | 59.090ms | 39 | 50 | 78.00 |
| V2 | jump | aon_timer_jump | 1.480s | 531.770us | 41 | 50 | 82.00 |
| V2 | stress_all | aon_timer_stress_all | 7.567m | 323.941ms | 41 | 50 | 82.00 |
| V2 | intr_test | aon_timer_intr_test | 1.300s | 464.615us | 40 | 50 | 80.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.470s | 899.412us | 13 | 20 | 65.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.470s | 899.412us | 13 | 20 | 65.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.660s | 726.127us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.260s | 497.175us | 14 | 20 | 70.00 | ||
| aon_timer_csr_aliasing | 1.630s | 696.319us | 4 | 5 | 80.00 | ||
| aon_timer_same_csr_outstanding | 6.150s | 1.663ms | 14 | 20 | 70.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.660s | 726.127us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.260s | 497.175us | 14 | 20 | 70.00 | ||
| aon_timer_csr_aliasing | 1.630s | 696.319us | 4 | 5 | 80.00 | ||
| aon_timer_same_csr_outstanding | 6.150s | 1.663ms | 14 | 20 | 70.00 | ||
| V2 | TOTAL | 188 | 240 | 78.33 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 4.290s | 4.458ms | 4 | 5 | 80.00 |
| aon_timer_tl_intg_err | 7.950s | 4.748ms | 13 | 20 | 65.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 7.950s | 4.748ms | 13 | 20 | 65.00 |
| V2S | TOTAL | 17 | 25 | 68.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 13.449m | 285.124ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 321 | 430 | 74.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 1 | 12.50 |
| V2 | 6 | 6 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.56 | 99.82 | 95.32 | 100.00 | -- | 99.35 | 100.00 | 96.90 |
Exit reason: Error: User command failed Job returned non-zero exit code has 96 failures:
Test aon_timer_prescaler has 11 failures.
0.aon_timer_prescaler.105614963034501189839057797446588421532771845586226968241099944106348529302230
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_prescaler/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_prescaler/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915651286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.915651286
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.aon_timer_prescaler.110650042956329068224159343534627741902142797764886393355288266720159053742485
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_prescaler/latest/run.log
[make]: simulate
cd /workspace/6.aon_timer_prescaler/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882554773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1882554773
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 9 more failures.
Test aon_timer_jump has 9 failures.
0.aon_timer_jump.75082287075624365387437182568503150963525442571084830007791230057794657505670
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_jump/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_jump/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461716870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2461716870
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
20.aon_timer_jump.63198655575536690990443871487519046207151004089275971791761464226500173064025
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_jump/latest/run.log
[make]: simulate
cd /workspace/20.aon_timer_jump/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908893529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1908893529
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 7 more failures.
Test aon_timer_stress_all_with_rand_reset has 12 failures.
0.aon_timer_stress_all_with_rand_reset.115487608127944926258564050674151250612053990073623414134701401151980242986991
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722962927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3722962927
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.aon_timer_stress_all_with_rand_reset.2007068617624150420357102646816824051486693016264636113189597524210544531964
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/7.aon_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678577660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2678577660
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 10 more failures.
Test aon_timer_sec_cm has 1 failures.
0.aon_timer_sec_cm.69593077561443849323262220458846854993745713301999864754741106656121747090420
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844732404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2844732404
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test aon_timer_mem_walk has 3 failures.
0.aon_timer_mem_walk.26037575497214723911329764773107861641362825574629216119061819894363352494819
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest/run.log
[make]: simulate
cd /workspace/0.aon_timer_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405566179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.405566179
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.aon_timer_mem_walk.54008865742802825752570992105038690490941963479156346667990567805250294162597
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest/run.log
[make]: simulate
cd /workspace/2.aon_timer_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277839013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.4277839013
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
... and 11 more tests.
Job aon_timer-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
Test aon_timer_tl_intg_err has 4 failures.
4.aon_timer_tl_intg_err.20731410135935104958680002347754073058939760771499993154417746536187043395071
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest/run.log
Job ID: smart:8cccd033-2842-4daf-a409-deb3fd47dea9
10.aon_timer_tl_intg_err.19058551149835745451331209697711282913131929272618399711389327460881216835210
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest/run.log
Job ID: smart:069a590f-c59f-4f4d-a9e4-212f78d426be
... and 2 more failures.
Test aon_timer_intr_test has 1 failures.
5.aon_timer_intr_test.85319295602505841011499395169807117606955571300391949075491717041379565056990
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_intr_test/latest/run.log
Job ID: smart:1c3edbd9-c9ae-4608-b809-ec27c714463a
Test aon_timer_same_csr_outstanding has 1 failures.
5.aon_timer_same_csr_outstanding.45542317704385064182672268457830158611056473028707299297157195713938707843072
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest/run.log
Job ID: smart:34f35200-b748-486a-8c10-effec354a016
Test aon_timer_csr_mem_rw_with_rand_reset has 1 failures.
9.aon_timer_csr_mem_rw_with_rand_reset.12645235296122252369154723088183601175783559351047122526978705945678869327368
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest/run.log
Job ID: smart:603aa8a7-4f95-4fd5-b20f-c82e9bd8242a
Test aon_timer_csr_rw has 1 failures.
15.aon_timer_csr_rw.53009167277984961068444845409734650860885363218622785172656333764052604601129
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest/run.log
Job ID: smart:ef39bb49-7098-4982-857a-e4303030b881
Job aon_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test aon_timer_stress_all_with_rand_reset has 3 failures.
5.aon_timer_stress_all_with_rand_reset.18977218325402593355826990467633816731804676166848276368250570408145492551982
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a8f932ae-3669-4145-afd0-3f0e310cc89e
8.aon_timer_stress_all_with_rand_reset.79499634943176889858921082459825836909734798104338714927649192453683957445969
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ac03110d-b67e-43a5-ba96-ba5cfd377536
... and 1 more failures.
Test aon_timer_stress_all has 1 failures.
30.aon_timer_stress_all.99635746620765515661478802781928296374207491947142401677883255200700015435222
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all/latest/run.log
Job ID: smart:746c20ef-516d-4c83-a918-acebfc6e4cbc
Test aon_timer_smoke has 1 failures.
42.aon_timer_smoke.101172213534276400795194981259106253462152427218339657796817263834161953411412
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_smoke/latest/run.log
Job ID: smart:2bc9f87a-fa8d-4a4e-95fb-a1011379f27c