AON_TIMER Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	573.468us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.730s	852.286us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.420s	514.952us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	11.440s	4.200ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.550s	554.493us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.460s	541.122us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.420s	514.952us	20	20	100.00
		aon_timer_csr_aliasing	1.550s	554.493us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.310s	479.279us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.060s	307.491us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.227m	50.262ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	549.567us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.767m	386.223ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	514.087us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.900s	947.842us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.900s	947.842us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.730s	852.286us	5	5	100.00
		aon_timer_csr_rw	1.420s	514.952us	20	20	100.00
		aon_timer_csr_aliasing	1.550s	554.493us	5	5	100.00
		aon_timer_same_csr_outstanding	7.630s	2.063ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.730s	852.286us	5	5	100.00
		aon_timer_csr_rw	1.420s	514.952us	20	20	100.00
		aon_timer_csr_aliasing	1.550s	554.493us	5	5	100.00
		aon_timer_same_csr_outstanding	7.630s	2.063ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.040s	7.907ms	5	5	100.00
		aon_timer_tl_intg_err	14.230s	8.187ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.230s	8.187ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.012m	121.962ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			429	430	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.61	99.82	95.32	100.00	--	99.35	100.00	97.16

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:315) [scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (* [*] vs * [*]) has 1 failures:
  • Test aon_timer_stress_all has 1 failures.

    • 34.aon_timer_stress_all.74590383022631164578673535578687230444095933721421076643462545057871515080874
      Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all/latest/run.log

        UVM_ERROR @ 466343416004 ps: (aon_timer_scoreboard.sv:315) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 466343416004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.01.11_02.58.37
• 2024.01.08_02.45.50
• 2024.01.04_01.09.53
• 2024.01.01_00.37.33
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• 2023.12.25_01.14.22
• 2023.12.21_00.01.50