AON_TIMER Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.470s 588.656us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.560s 1.185ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.430s 489.578us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 12.560s 5.815ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.340s 502.515us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.490s 564.347us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.430s 489.578us 20 20 100.00
aon_timer_csr_aliasing 1.340s 502.515us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.290s 463.079us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.350s 503.151us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.756m 61.888ms 50 50 100.00
V2 jump aon_timer_jump 1.540s 595.502us 50 50 100.00
V2 stress_all aon_timer_stress_all 8.488m 308.699ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.360s 506.624us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.710s 509.058us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.710s 509.058us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.560s 1.185ms 5 5 100.00
aon_timer_csr_rw 1.430s 489.578us 20 20 100.00
aon_timer_csr_aliasing 1.340s 502.515us 5 5 100.00
aon_timer_same_csr_outstanding 5.540s 1.968ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.560s 1.185ms 5 5 100.00
aon_timer_csr_rw 1.430s 489.578us 20 20 100.00
aon_timer_csr_aliasing 1.340s 502.515us 5 5 100.00
aon_timer_same_csr_outstanding 5.540s 1.968ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 13.730s 8.386ms 5 5 100.00
aon_timer_tl_intg_err 14.600s 8.585ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 14.600s 8.585ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 15.273m 545.777ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.56 99.82 95.32 100.00 -- 99.35 100.00 96.90

Past Results