AON_TIMER Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.500s 584.288us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.860s 1.480ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.470s 540.451us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 9.090s 7.527ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.620s 657.090us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.460s 507.518us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.470s 540.451us 20 20 100.00
aon_timer_csr_aliasing 1.620s 657.090us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.180s 457.451us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.150s 406.495us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.264m 52.604ms 50 50 100.00
V2 jump aon_timer_jump 1.530s 634.802us 50 50 100.00
V2 stress_all aon_timer_stress_all 10.652m 449.606ms 49 50 98.00
V2 intr_test aon_timer_intr_test 1.360s 511.654us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.610s 806.688us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.610s 806.688us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.860s 1.480ms 5 5 100.00
aon_timer_csr_rw 1.470s 540.451us 20 20 100.00
aon_timer_csr_aliasing 1.620s 657.090us 5 5 100.00
aon_timer_same_csr_outstanding 6.620s 2.358ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.860s 1.480ms 5 5 100.00
aon_timer_csr_rw 1.470s 540.451us 20 20 100.00
aon_timer_csr_aliasing 1.620s 657.090us 5 5 100.00
aon_timer_same_csr_outstanding 6.620s 2.358ms 20 20 100.00
V2 TOTAL 239 240 99.58
V2S tl_intg_err aon_timer_sec_cm 11.920s 8.280ms 5 5 100.00
aon_timer_tl_intg_err 15.400s 8.393ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 15.400s 8.393ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 15.270m 81.263ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 429 430 99.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.82 95.31 100.00 -- 99.35 100.00 96.64

Failure Buckets

Past Results