AON_TIMER Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	624.114us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.410s	1.204ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	546.353us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.630s	13.865ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.520s	516.201us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	539.028us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	546.353us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	516.201us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.990s	353.852us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.290s	516.124us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.435m	60.347ms	50	50	100.00
V2	jump	aon_timer_jump	1.600s	580.987us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.581m	531.491ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.310s	501.705us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.920s	491.433us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.920s	491.433us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.410s	1.204ms	5	5	100.00
		aon_timer_csr_rw	1.370s	546.353us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	516.201us	5	5	100.00
		aon_timer_same_csr_outstanding	7.420s	2.883ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.410s	1.204ms	5	5	100.00
		aon_timer_csr_rw	1.370s	546.353us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	516.201us	5	5	100.00
		aon_timer_same_csr_outstanding	7.420s	2.883ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	12.940s	7.912ms	5	5	100.00
		aon_timer_tl_intg_err	13.540s	8.655ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.540s	8.655ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.348m	120.881ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

10.aon_timer_stress_all_with_rand_reset.85789777864919394855942565178016327605483599879991306605980802898445293845449
Line 262, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 779211919 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 779211919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.aon_timer_stress_all_with_rand_reset.92108272334052641743706564376940181967684109422397870972410605622465806432132
Line 272, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 865856762 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 865856762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 2 failures.

27.aon_timer_stress_all.105475007008458982129735877076332331846750935305432876801149455090654734648140
Line 282, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 21200158748 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 21200158748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aon_timer_stress_all.39206878071305138035396377908285541004655142253321275904867503867895619963013
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 53660998760 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 53660998760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---