AON_TIMER Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: 1f410ef5dc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 0 50 0.00
V1 csr_hw_reset aon_timer_csr_hw_reset 0 5 0.00
V1 csr_rw aon_timer_csr_rw 0 20 0.00
V1 csr_bit_bash aon_timer_csr_bit_bash 0 5 0.00
V1 csr_aliasing aon_timer_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 0 20 0.00
aon_timer_csr_aliasing 0 5 0.00
V1 mem_walk aon_timer_mem_walk 0 5 0.00
V1 mem_partial_access aon_timer_mem_partial_access 0 5 0.00
V1 TOTAL 0 115 0.00
V2 prescaler aon_timer_prescaler 0 50 0.00
V2 jump aon_timer_jump 0 50 0.00
V2 stress_all aon_timer_stress_all 0 50 0.00
V2 intr_test aon_timer_intr_test 0 50 0.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 0 20 0.00
V2 tl_d_illegal_access aon_timer_tl_errors 0 20 0.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 0 5 0.00
aon_timer_csr_rw 0 20 0.00
aon_timer_csr_aliasing 0 5 0.00
aon_timer_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 0 5 0.00
aon_timer_csr_rw 0 20 0.00
aon_timer_csr_aliasing 0 5 0.00
aon_timer_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 240 0.00
V2S tl_intg_err aon_timer_sec_cm 0 5 0.00
aon_timer_tl_intg_err 0 20 0.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 0 20 0.00
V2S TOTAL 0 25 0.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 0 430 0.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 0 0.00
V2 6 6 0 0.00
V2S 2 2 0 0.00
V3 1 1 0 0.00

Failure Buckets

Past Results