AON_TIMER Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	457.451us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.270s	1.283ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.250s	484.023us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.120s	9.834ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.710s	680.134us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	512.524us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.250s	484.023us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	680.134us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.220s	472.252us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.040s	414.863us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.494m	58.070ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	582.832us	50	50	100.00
V2	stress_all	aon_timer_stress_all	21.509m	769.693ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.300s	414.352us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.710s	429.016us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.710s	429.016us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.270s	1.283ms	5	5	100.00
		aon_timer_csr_rw	1.250s	484.023us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	680.134us	5	5	100.00
		aon_timer_same_csr_outstanding	5.060s	2.500ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.270s	1.283ms	5	5	100.00
		aon_timer_csr_rw	1.250s	484.023us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	680.134us	5	5	100.00
		aon_timer_same_csr_outstanding	5.060s	2.500ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	12.160s	7.561ms	5	5	100.00
		aon_timer_tl_intg_err	15.080s	8.951ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.080s	8.951ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.387m	178.228ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.02	99.25	93.67	100.00	--	98.40	99.51	67.30

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 11 failures.

0.aon_timer_stress_all_with_rand_reset.48482672583465303424421526206928627389587186743031906823525103269999707009867
Line 673, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 232851303378 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 232851303378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aon_timer_stress_all_with_rand_reset.100146922421087527908023817080637359022307800736414568752049565156866722086269
Line 1079, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 435120245271 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 435120245271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test aon_timer_stress_all has 2 failures.

11.aon_timer_stress_all.63564712344602013142960532141990052361619515798007997245363422946525330163300
Line 299, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 93403386873 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 93403386873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aon_timer_stress_all.71766841127487117497719666676892401421292625122122308215204768579309337680440
Line 298, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 87361279525 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 87361279525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---