AON_TIMER Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	575.579us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.040s	1.176ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	501.672us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	16.080s	13.494ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.880s	582.617us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.580s	605.534us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	501.672us	20	20	100.00
		aon_timer_csr_aliasing	1.880s	582.617us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.080s	357.278us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.020s	302.218us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.505m	57.115ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	570.663us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.192m	599.372ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.470s	507.931us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.700s	523.925us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.700s	523.925us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.040s	1.176ms	5	5	100.00
		aon_timer_csr_rw	1.300s	501.672us	20	20	100.00
		aon_timer_csr_aliasing	1.880s	582.617us	5	5	100.00
		aon_timer_same_csr_outstanding	5.860s	2.530ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.040s	1.176ms	5	5	100.00
		aon_timer_csr_rw	1.300s	501.672us	20	20	100.00
		aon_timer_csr_aliasing	1.880s	582.617us	5	5	100.00
		aon_timer_same_csr_outstanding	5.860s	2.530ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	8.090s	4.835ms	5	5	100.00
		aon_timer_tl_intg_err	14.600s	8.685ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.600s	8.685ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.964m	188.251ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 5 failures.

3.aon_timer_stress_all_with_rand_reset.30007686313224807338375225146068788389355826398224123357225373631088545181575
Line 601, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 89401420033 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 89401420033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aon_timer_stress_all_with_rand_reset.45116881467559069295476860402267108370822726072489485731910870827769967428117
Line 1254, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 247887526438 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 247887526438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all has 5 failures.

11.aon_timer_stress_all.75464399224882487840510099367690115200509758981738704229778742257054749267033
Line 268, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 101325427701 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 101325427701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all.13788772010925443744694826843907797000789055232972933159503275551327939597116
Line 282, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 117397069616 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 117397069616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.