AON_TIMER Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.370s	490.853us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.560s	1.203ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.610s	550.924us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.940s	13.852ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.130s	403.154us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.500s	629.044us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.610s	550.924us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	403.154us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.200s	448.920us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.040s	348.152us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.716m	61.204ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	609.362us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.370m	848.895ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.360s	474.274us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.810s	543.836us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.810s	543.836us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.560s	1.203ms	5	5	100.00
		aon_timer_csr_rw	1.610s	550.924us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	403.154us	5	5	100.00
		aon_timer_same_csr_outstanding	8.150s	2.111ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.560s	1.203ms	5	5	100.00
		aon_timer_csr_rw	1.610s	550.924us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	403.154us	5	5	100.00
		aon_timer_same_csr_outstanding	8.150s	2.111ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	7.880s	8.787ms	5	5	100.00
		aon_timer_tl_intg_err	15.960s	8.298ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.960s	8.298ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.824m	624.457ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.96150846411254559856644890942889977996404896178169899965572036324741444936984
Line 478, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 76855502628 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 76855502628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.aon_timer_stress_all_with_rand_reset.74267170741476275793098689989339072142366505957147254211795763707055211835832
Line 1005, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 150546008321 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 150546008321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 4 failures.

6.aon_timer_stress_all.65352798503404397862004372866512655174451529890536878428856232997479192006013
Line 272, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 57591583864 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 57591583864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.6212036778718766043198868509389529182485790266226992109461951148371867367839
Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 51011986126 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 51011986126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.