AON_TIMER Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	593.072us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.090s	1.025ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.390s	515.675us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.510s	7.334ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.420s	535.377us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.650s	589.683us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.390s	515.675us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	535.377us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.910s	508.505us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.170s	419.540us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.510m	58.588ms	50	50	100.00
V2	jump	aon_timer_jump	1.570s	582.135us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.506m	413.592ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.390s	474.982us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.850s	594.657us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.850s	594.657us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.090s	1.025ms	5	5	100.00
		aon_timer_csr_rw	1.390s	515.675us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	535.377us	5	5	100.00
		aon_timer_same_csr_outstanding	5.170s	2.883ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.090s	1.025ms	5	5	100.00
		aon_timer_csr_rw	1.390s	515.675us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	535.377us	5	5	100.00
		aon_timer_same_csr_outstanding	5.170s	2.883ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	5.230s	8.374ms	5	5	100.00
		aon_timer_tl_intg_err	15.110s	8.392ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.110s	8.392ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.821m	237.320ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

7.aon_timer_stress_all_with_rand_reset.93935004874532641169686570071292657034574728011891099160117401039603361121671
Line 507, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25700484631 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 25700484631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all_with_rand_reset.110021741247783073152257740848911055242399616968930490666735827919855204455912
Line 1127, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 137607758726 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 137607758726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 1 failures.

23.aon_timer_stress_all.36397478316513308070127912594999609941288700032897256343732343821885067778252
Line 294, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 68149400951 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 68149400951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:368) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 19.aon_timer_stress_all.53173368919265673204419388692514086690833803255670166061007184186637152521193
    Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 888031910 ps: (aon_timer_scoreboard.sv:368) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 888031910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```