AON_TIMER Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	591.419us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.440s	951.154us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	526.104us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	50.700s	12.682ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.320s	450.388us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.610s	615.786us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	526.104us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	450.388us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.050s	345.664us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.940s	280.775us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.501m	55.160ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	563.305us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.832m	260.719ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.300s	480.893us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.740s	404.508us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.740s	404.508us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.440s	951.154us	5	5	100.00
		aon_timer_csr_rw	1.380s	526.104us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	450.388us	5	5	100.00
		aon_timer_same_csr_outstanding	4.460s	2.826ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.440s	951.154us	5	5	100.00
		aon_timer_csr_rw	1.380s	526.104us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	450.388us	5	5	100.00
		aon_timer_same_csr_outstanding	4.460s	2.826ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	9.220s	8.345ms	5	5	100.00
		aon_timer_tl_intg_err	15.140s	8.699ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.140s	8.699ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.133m	902.082ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 11 failures.

0.aon_timer_stress_all_with_rand_reset.38010138848459044536734684774846674492854681935072797350169628527077026440659
Line 291, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1309394849 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1309394849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aon_timer_stress_all_with_rand_reset.25776295561003272760449098138027915428340763210870920646120656903217829208465
Line 979, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 253780440316 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 253780440316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test aon_timer_stress_all has 2 failures.

22.aon_timer_stress_all.52880303216125660896328317215541438592934966554903617203496993429804452787522
Line 287, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 260719300933 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 260719300933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.aon_timer_stress_all.109536964221847240493127536760083170174381214021618615216556289609978005231480
Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 340456174 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 340456174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---