AON_TIMER Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	581.631us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.460s	637.354us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.520s	501.382us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	30.660s	13.864ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.910s	698.553us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	575.915us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.520s	501.382us	20	20	100.00
		aon_timer_csr_aliasing	1.910s	698.553us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.310s	473.123us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	507.506us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.401m	51.030ms	50	50	100.00
V2	jump	aon_timer_jump	1.560s	579.808us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.854m	482.490ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.380s	503.026us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.820s	497.930us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.820s	497.930us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.460s	637.354us	5	5	100.00
		aon_timer_csr_rw	1.520s	501.382us	20	20	100.00
		aon_timer_csr_aliasing	1.910s	698.553us	5	5	100.00
		aon_timer_same_csr_outstanding	3.750s	2.238ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.460s	637.354us	5	5	100.00
		aon_timer_csr_rw	1.520s	501.382us	20	20	100.00
		aon_timer_csr_aliasing	1.910s	698.553us	5	5	100.00
		aon_timer_same_csr_outstanding	3.750s	2.238ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	13.460s	8.078ms	5	5	100.00
		aon_timer_tl_intg_err	13.480s	8.104ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.480s	8.104ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.708m	481.968ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

0.aon_timer_stress_all_with_rand_reset.87494130538767276790337958446265975588444319302008163355617692829225060674441
Line 751, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 77354115879 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 77354115879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all_with_rand_reset.108354546882384660999515864050371676372294438453677654072754020110970881327093
Line 700, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 67173595889 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 67173595889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 3 failures.

10.aon_timer_stress_all.80075584974768322440643602393692715751398573970477371684528209182316909628015
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 19370069796 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 19370069796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.aon_timer_stress_all.7140529154414751698878854120716075143525553565564570541394222548323345227113
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 3809405023 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3809405023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.