CLKMGR Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.660s	315.483us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.870s	19.493us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.180s	1.055ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.750s	106.653us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.800s	291.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
		clkmgr_csr_aliasing	1.750s	106.653us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.970s	109.918us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.660s	322.388us	50	50	100.00
V2	extclk	clkmgr_extclk	1.320s	200.549us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	137.838us	50	50	100.00
V2	jitter	clkmgr_smoke	1.660s	315.483us	50	50	100.00
V2	frequency	clkmgr_frequency	18.030s	2.476ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.070s	2.419ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.030s	2.476ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.180m	10.540ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.850s	78.631us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.130s	173.170us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.980s	463.289us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.980s	463.289us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.870s	19.493us	5	5	100.00
		clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
		clkmgr_csr_aliasing	1.750s	106.653us	5	5	100.00
		clkmgr_same_csr_outstanding	1.780s	218.094us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.870s	19.493us	5	5	100.00
		clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
		clkmgr_csr_aliasing	1.750s	106.653us	5	5	100.00
		clkmgr_same_csr_outstanding	1.780s	218.094us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.820s	1.258ms	5	5	100.00
		clkmgr_tl_intg_err	6.200s	1.700ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.210s	1.116ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.210s	1.116ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.210s	1.116ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.210s	1.116ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	6.560s	1.547ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.200s	1.700ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.030s	2.476ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.070s	2.419ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.210s	1.116ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.260s	487.463us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.250s	154.936us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.530s	280.915us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.320s	175.959us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.100s	128.020us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.820s	1.258ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.010s	61.497us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.820s	1.258ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.037m	427.660ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			959	960	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.12	95.44	100.00	100.00	98.71	96.97	93.18

Failure Buckets

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 11.clkmgr_stress_all_with_rand_reset.3708206309
      Line 2722, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 71037425484 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 71037425484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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