CLKMGR Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.470s	224.592us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.030s	133.266us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.460s	1.438ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.330s	285.679us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.000s	61.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
		clkmgr_csr_aliasing	2.330s	285.679us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.250s	192.942us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.970s	400.087us	50	50	100.00
V2	extclk	clkmgr_extclk	1.370s	229.657us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.110s	176.599us	50	50	100.00
V2	jitter	clkmgr_smoke	1.470s	224.592us	50	50	100.00
V2	frequency	clkmgr_frequency	19.100s	2.361ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	14.730s	2.058ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.100s	2.361ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.696m	14.666ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.940s	141.823us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.500s	261.277us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.250s	471.808us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.250s	471.808us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.030s	133.266us	5	5	100.00
		clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
		clkmgr_csr_aliasing	2.330s	285.679us	5	5	100.00
		clkmgr_same_csr_outstanding	1.800s	201.588us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.030s	133.266us	5	5	100.00
		clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
		clkmgr_csr_aliasing	2.330s	285.679us	5	5	100.00
		clkmgr_same_csr_outstanding	1.800s	201.588us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.130s	690.854us	5	5	100.00
		clkmgr_tl_intg_err	5.730s	1.238ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.660s	378.300us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.660s	378.300us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.660s	378.300us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.660s	378.300us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.370s	1.176ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.730s	1.238ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.100s	2.361ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	14.730s	2.058ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.660s	378.300us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.070s	344.975us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.440s	223.903us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.650s	301.640us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.400s	241.007us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.320s	182.972us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.130s	690.854us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.060s	127.787us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.130s	690.854us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.300s	1.249ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	45.636m	771.728ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 6.clkmgr_stress_all_with_rand_reset.29734616542280683296949007675801681461603566533393969121582589052235708523283
      Line 588, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 9544444540 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 9544444540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 21.clkmgr_stress_all_with_rand_reset.52199977632119550633740940933548623108309206487466445834722418373708423923780
      Line 607, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 5992422528 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 5992422528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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